Embedded Solutions
Page 25
pmcparttl_IntRisLstat
$54 Falling Status Lower Control Register Port read/write
DATA BIT
DESCRIPTION
31-0
Falling COS Status bits 31-0
Figure 24
PMC-PARALLEL-TTL Falling COS Status Lower
pmcparttl_IntRisUstat
$58 Falling Status Upper Control Register Port read/write
DATA BIT
DESCRIPTION
31-0
Falling COS Status bits 63-32
Figure 25
PMC-PARALLEL-TTL Falling COS status upper
The COS captured for those bits enabled with the Falling register are held in this
register. The bits are held until cleared. The bits are cleared by writing to the register
with the corresponding bit or bits set. Writing to the register with the data read will clear
the bits the software has read, and not clear the bits not set at the time of reading. This
is the recommended practice to avoid conflicts. It is recommended to write to all bits
[clear] after setting the COS Falling and Direction bits to clear any potential COS status
generated by set-up.
