Embedded Solutions
Page 7
programmable to use the reference rate or to divide it to a lower frequency. An optional
PLL capability is available for users who require more extensive frequency options.
All of the IO are routed through the FPGA to allow for custom applications that require
hardware intervention or specific timing- for example an automatic address or data
strobe to be generated. The initial model is register based. The design is DMA
capable and can be used for more intensive applications of data capture or delivery.
Please contact Dynamic Engineering with your requirements.
The IO are driven with open-drain high current drivers. When enabled, the high side is
driven with the device and augmented with pull-up resistors. When disabled the output
is pulled high with the resistors unless another device on the line is driving that line low.
The low side of the driver can sink 64+ mA. The high side drive is a few mA. All IO
have 2 pull-up locations per line. The default is for 470 ohms installed into one location.
The multiple locations allow for pull-up strengths greater than 470 ohms, and to stay
within the resistor pack wattage capabilities. The multiple packs also allow for parallel
combinations to create more options of specific pull-up values. For custom models with
additional pull-ups or alternate values please contact Dynamic Engineering. The two
columns of pull-up resistor locations are visible on the rear of the card.
Figure 1
PMC-PARALLEL-TTL REAR VIEW
The registers are mapped as 32 bit words and support byte, word and 32 bit access. All
registers are read-writeable. The Windows® compatible [XP/2000] driver is available to
provide the system level interface for this design. Use standard C/C++ to control your
hardware or use the Hardware manual to make your own software interface. The
software manual is also available on-line.
The basic functions of parallel IO and COS capture are designed into the base model.
Additional features will be added to the base model by using a mux on the output side to
allow software to select the base or extended features. Data bit 0 is the first extended
feature and is a programmable output for the COS reference clock. With software the
output definition can be changed to drive the COS clock onto Data 0. The user can use
a scope to check that their set-up is what they want it to be and then likely return it to
being a data bit. You can leave is as a clock if desired. Additional features will be
incorporated into the base design in a manner where the default is the initial base
