Embedded Solutions
Page 17
pmcparttl_DatL
[$14 Data IO Port read/write]
DATA BIT
DESCRIPTION
31-0
Data IO 31-0
Figure 9
PMC-PARALLEL-TTL Data IO Lower Bit Map
pmcparttl_DatU
[$18 Data IO Port read/write]
DATA BIT
DESCRIPTION
31-0
Data IO 63-32
Figure 10
PMC-PARALLEL-TTL Data IO Upper Bit Map
This port is really a combined Data Output port and a Data Input port. The data to be
transmitted is written to the Data Output Port side of the Data Register. The data to be
read from the IO are read from Data Input side of the Data register. Read back from the
Data Output port is done though the separate “datareg” port.
The data read from the data register is a direct read of the state of the IO lines. The bits
are not modified for level or transition etc. Some bits may be defined as outputs. The
input will match the output definition in this case. Local loop-back can be performed for
the bits where outputs are defined. The inputs will match the state of the system when
external devices can drive the input lines. The input bits can be masked out of the data
word to reduce the data to external inputs.
The output bits are driven onto the outputs for the bits which are enabled with the
direction control register and when the master parallel enable is set. For bits without the
direction register bit set there are no side effects. The direction register will act as a
mask for the data register.
