Embedded Solutions
Page 9
Theory of Operation
The PMC-PARALLEL-TTL can be used for multiple purposes with applications in
telecommunications, control, sensors, IO, test; anywhere multiple independent IO are
useful.
The PMC-PARALLEL-TTL features a Xilinx FPGA, and high current LVTH driver
devices. The FPGA contains the PCI interface and control required for the parallel
interface.
The Xilinx design incorporates the “PCI Core” and additional modules for DMA in
parallel with a direct register decoded programming model. The initial implementation
provides an enhanced feature set based on the PMC Parallel IO design. Additional
FLASH updates will provide DMA, pattern generation, pulse generation, and user
defined requirements.
The drivers are initialized to the off state and pull-ups on board hold the IO lines in the
‘high’ state. The direction registers are used to program the channel to be a driver or
not. The receivers are always enabled allowing local read-back of the transmitted data.
Data written to the IO registers can be placed on the bus. The master enable allows all
64 channels to be synchronized if desired. The master enable can be programmed “on”
to allow direct updates if 64 bit synchronization is not required.
For an IO with the direction bit set and master enabled: When a ‘0’ is written to any IO
line register position the corresponding line is driven low. When a ‘1’ is written to any IO
line register position that line is un-driven by the local driver and the output level will be
controlled by the termination resistor, and any other drivers attached to that line. The
control register is read-writeable. The data register read corresponds to the IO side.
The register read-back is at an alternate address offset. The register read-back is
independent of the bus; the data read will always match the data written. The IO data
read will reflect the state of the bus and not necessarily the state of the on-board
drivers.
The read-back registers are clocked at a programmable rate with an internal clock
generator. If desired the internal clock can be replaced with an external source and an
enable. The basic option is available under SW control. If special programming is
needed please contact Dynamic Engineering for a custom FPGA implementation.
All the IO control and registers are instantiated within the FPGA, only the drivers and
receivers are separate devices. If desired, the IO lines can be specially programmed
to create custom timing pulses etc. For example if the interface is to put out an address
