DY 4 Systems Inc.
Product Overview
809789 Revision 2 December 2000
1-5
Technical Description
Clock Circuitry
Clock reference circuitry on the PMC-700-X00 generates a 14.318 MHz clock
to drive the Permedia3.
Permedia3
The Permedia3 is a high performance graphics processor designed to
accelerate 3D and 2D applications. It provides 3D polygon and textured
graphics acceleration. It has a fast integrated SVGA core and integrated
RAMDAC. It includes hardware support for OpenGL.
Reset
The Permedia3 resets when the basecard asserts the PCI_RST* signal. The
reset status of the Permedia3 is controlled through the use of configuration
resistors. After reset, the Permedia3 is in the following state:
•
internal VGA subsystem is present;
•
VGA Fixed address decoding is enabled;
•
PCI Retry using “Disconnected Without Data” is disabled;
•
the upper half of region Zero is write-combined;
•
Base Address Registers 1 and 2 (representing relocatable address spaces
Memory Aperture One and Two respectively) are marked as prefetcha-
ble.
PCI Bus Interface
The Permedia3 implements the PCI bus interface and is compliant with the PCI
Local Bus standard Revision 2.1. Protection diodes protect the Permedia3
device from signal overshoot.
Data Path
The data path into and out of the PMC-700-X00 supports 8, 16, and 32-bit data
transfers. That is, as a slave, the PMC-700-X00 provides D32, D16, and D8
interfaces.
PCI Bus Interrupts
A single PCI bus interrupt is generated as part of the Permedia3 PCI bus
implementation. The interrupt level and vector are programmable by the
basecard CPU. The interrupt is initialized and serviced by the X Server
software.
PCI Bus
Arbitration
The Permedia3 acts as a PCI Local Bus Target, a PCI Local Bus Read Master,
and a PCI Local Bus Write Master. All PCI bus arbitration is resolved as per
3DLabs’ implementation of the PCI specification.
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