Diversified Technology CPB-4612 Configuration And Maintenance Manual Download Page 37

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4.1.4 NMI

Sources

Watchdog Timer (System Register Address 79h)

The watchdog timer may be programmed to generate a non-maskable interrupt if it is not strobed within a
given time-out period. This function is discussed in Chapter 7, "Watchdog Timer."

Summary of Contents for CPB-4612

Page 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Page 2: ...opyright 2005 by Diversified Technology Inc All rights reserved Printed in the United States of America No part of this publication may be reproduced stored in a retrieval system or transmitted in any...

Page 3: ...original shipping materials Contact DTI if replacement material is required Seal the carton securely and ship prepaid to the following address with the RMA number on the label DIVERSIFIED TECHNOLOGY...

Page 4: ...plosion if the battery is incorrectly replaced or handled Do not disassemble or recharge the battery Do not dispose of the battery in fire When the battery is replaced the same type or an equivalent t...

Page 5: ...Maintenance Guide iv Revision History Date Revision Summary of Corrections 08 31 04 1 0 Initial Release 10 12 04 1 1 Added links throughout manual 8 19 05 1 2 Removed references to ethernet signal ro...

Page 6: ...PCI Mezzanine Card PMC Interface 7 1 3 10 Dual 10 100 1000 Ethernet Interfaces 7 1 3 11 10 100 Ethernet Interface 8 1 3 12 IDE Hard Drive 8 1 3 13 Serial I O 8 1 3 14 Interrupts 8 1 3 15 Counter Time...

Page 7: ...kend Power Down Sources 25 4 1 4 NMI Sources 26 5 SYSTEM MONITORING AND CONTROL 27 5 1 Monitoring and Control Functions 28 Figure 5 1 Packet Structure 28 5 2 IPMB 28 5 3 Field Replaceable Unit FRU Inf...

Page 8: ...8 2 5 IDE Config 46 8 2 6 Hard Disk Setup 47 8 2 7 Boot Order 49 8 2 8 Peripherals 51 8 2 9 USB Configuration 53 8 2 10 MISC Config 55 8 2 11 Event Logging 57 8 2 12 Security Virus 58 8 2 13 Exit 59...

Page 9: ...12 and J13 32bit 33Mhz PCI Mezzanine Connectors 80 B 11 J14 IDE Connector 82 C THERMAL CONSIDERATIONS 84 C 1 Thermal Requirements 85 C 2 Temperature Monitoring 85 D DATASHEET REFERENCE 88 D 1 CompactP...

Page 10: ...72 J8 Connector Pin out 73 J2 Rear Panel I O Connector Pin out 74 J4 Universal Serial Bus 0 Connector Pin out 75 Thermal Requirements 85 Figures CPB 4612 Faceplate 3 Functional Block Diagram 5 Memory...

Page 11: ...arious system monitoring and control features available on the CPB 4612 Chapter 6 IDE Controller provides an introduction to the CPB 4612 s IDE Controller This chapter covers drive configuration IDE I...

Page 12: ...compatible rear panel transition boards see Appendix F The CPB 4612 is a 64 bit compliant CompactPCI Pentium M single board computer designed to operate in either a system slot or a peripheral slot T...

Page 13: ...compatible and draws its power from the J1 and J2 connectors The cPB 4612 includes an Intelligent Platform Management Bus IPMB for system management along with IPMI v1 5 compatible firmware The cPB 46...

Page 14: ...3 CPB 4612 Faceplate Ejector Handle Ejector Handle PMC PMC 10 100 Ethernet COM RS 232 Serial Port USB Hotswap LED Reset Switch...

Page 15: ...emory at 200 266 or 333 MHz Dual stage watchdog timer IPMI support Option for either a single on board PCI Mezzanine Card PMC slot 32 bit 33MHz or a primary IDE channel that supports an on board 2 5 i...

Page 16: ...transparent bridge and the board will perform as the host If the board is placed in a peripheral slot the bridge will automatically configure itself as a non transparent bridge and the board will per...

Page 17: ...micro architecture using proven and established building blocks 400MHz system bus delivers a high bandwidth connection between the Intel Pentium M and the platform providing 3x the bandwidth over plat...

Page 18: ...video is accessed through the CompactPCI J5 connector The 855GME can share up to 32MB of system memory with the internal video The onboard video from the Intel 855GME may be disabled by a jumper sett...

Page 19: ...upports a second ATA 100 IDE interface through the CompactPCI J5 connector The IDE interface is implemented using Intel s 6300ESB I O Controller Hub ICH All versions of the cPB 4612 supports a Serial...

Page 20: ...s 256 bytes of general purpose battery backed CMOS RAM Timekeeping features include an alarm function a maskable periodic interrupt and a 100 year calendar The system BIOS uses a portion of this RAM f...

Page 21: ...troller is accessed through an IPMB bus from the backplane See System Monitoring and Control in chapter 5 for more details 1 3 22 LED Indicators The LEDs located at the cPB 4612 s faceplate are define...

Page 22: ...11 Chapter 2 2 2 Getting Started This chapter summarizes the information needed to make the cPB 4612 operational This chapter should be read before using the board...

Page 23: ...ailed information 2 2 1 BIOS Version For proper operation the cPB 4612 must run the DTI enhanced AMI Embedded BIOS The revision level is shown in the BIOS Identification string displayed during the Po...

Page 24: ...le the cPB 4612 is installed in its intended location Insert a thermistor type air velocity meter Kane May KM4007 or similar through the PMC access on the faceplate and make the air velocity measureme...

Page 25: ...IOS Flash 8000000h FFF7FFFFh PCI PERIPHERALS 100000h 1FFFFFFFh SYSTEM MEMORY 4 GB 512 KB 512 MB 1 MB E0000h FFFFFh SYSTEM BIOS C8000h DFFFFh BIOS EXTENSION C0000h C7FFFh VGA BIOS A0000h BFFFFh VGA DIS...

Page 26: ...6 bit 3F0 3F7h Floppy IDE Registers I O space at the following 3E0 3EFh Reserved ranges 3B0 3DFh VGA Registers x100 x3FFh 380 3AFh Reserved x500 x7FFh 378 37Fh LPT x900 xBFFh 300 377h Reserved xD00 xF...

Page 27: ...tery backed RAM in the real time clock device and are used by the BIOS to initialize the system at boot up or reset The configuration is protected by a checksum word for system integrity To access the...

Page 28: ...ating system vendor 1 Install peripheral devices CompactPCI devices are automatically configured by the BIOS during the boot sequence 2 Most operating systems require initial installation on a hard dr...

Page 29: ...lect appropriate device types if prompted Refer to the appropriate hardware manuals for specific device types and compatibility modes of DTI products 6 When installation is complete reboot the system...

Page 30: ...ty Many features can be configured by the user for specific applications Most configuration options are selected through the BIOS Setup utility discussed in the BIOS Configuration Overview topic in Ch...

Page 31: ...described in the Jumper Cross Reference table below Factory default switch settings are shown in the Default Jumper Settings figure Jumper Cross Reference Table Jumper Function PB1 Reset push button o...

Page 32: ...discussed in more detail in Chapter 4 3 1 2 J16 1 BKT GND to GND Installing this jumper will short the bracket ground to digital ground This may positively or negatively affect EMI emissions dependin...

Page 33: ...setting Not placing the voltage key placing the voltage key at the wrong location or using a PMC card that is not tolerant of the set voltage may damage the PMC card and or the cPB 4612 board J16 3 C...

Page 34: ...a system that is powered on then the ejector handles should be opened just enough to disengage the handles from the chassis but without fully disengaging the J connectors from the back of the chassis...

Page 35: ...hapter 4 4 4 Reset This chapter discusses the reset types and reset sources on the cPB 4612 If necessary the cPB 4612 s board reset characteristics can be tailored to the requirements of a specific sy...

Page 36: ...CLK This causes the processor to enter real mode initialize its internal registers and begin instruction execution from FFFFFFF0h the boot vector Keyboard Controller Reset The keyboard controller gene...

Page 37: ...atchdog Timer System Register Address 79h The watchdog timer may be programmed to generate a non maskable interrupt if it is not strobed within a given time out period This function is discussed in Ch...

Page 38: ...Replaceable Unit FRU information and Sensor Device Records SDR s available Sensors monitor voltages CPU and system temperature and other inputs including the front latch which can generate events that...

Page 39: ...tructure otherwise is identical to the IPMB Figure 5 1 Packet Structure Because the serial interface in this case is dedicated the responder address and requester address bytes can be anything The IPM...

Page 40: ...BMC will generate sensor events on the IPMB These events will normally be logged by the BMC and time date stamped On temperature and voltage sensors if sensor readings cross any of the non critical cr...

Page 41: ...incorporated into the Intel 6300ESB which supports ATA 100 There is one 50 pin IDE connector on the cPB 4612 with IDE which supports up to two IDE devices though there is only space on the board itsel...

Page 42: ...compatible rear panel I O board Rear Panel I O boards such as the cRT 4612 can be installed in line behind the cPB 4612 to provide expanded I O capability Refer to the DTI PlexSys cRT 4612 Packet Swi...

Page 43: ...g Timer This chapter explains the operation of the cPB 4612 s watchdog timer It provides an overview of watchdog operation and features as well as sample code to help you learn how the watchdog timer...

Page 44: ...loaded with the first preload register The timer is then enabled and it starts counting down This is called the first stage If the counter reaches zero before being reloaded the watchdog timer generat...

Page 45: ...ing point of the 35 bit down counter 0 The 20 bit preload value is loaded into bits 34 15 of the main down counter The resulting timer clock is PCI clock 33MHz divided by 215 The approximate clock gen...

Page 46: ...Memory Mapped Registers The following registers control the preload values and reload status of the watchdog timer controller These register locations are offsets from the value of the base address r...

Page 47: ...rupt Active 7 3 4 Reload Register BAR 0Ch Offset BAR 0Ch Default Value 0000h Size 16 bits Attribute R W Bit Description 15 10 Reserved 9 WDT_TIMEOUT This bit lives in the RTC well and its value is not...

Page 48: ...ration Register Else if the value desired falls between 1 s and 1sec set bit 2 of the WDT Configuration Register 2 Write 80 to the memory mapped Reload Register offset BAR 0Ch 3 Write 86 to the memory...

Page 49: ...The BIOS contains standard PC compatible basic input output I O services and several DTI specific functions and features Support for applicable SBC peripheral devices SCSI NIC video adapters etc that...

Page 50: ...nts of the BIOS ROM are corrupted there is a mechanism to recover the BIOS Rom using the BIOS bootblock code To reprogram corrupted BIOS you should do the following 1 The latest flash will be distribu...

Page 51: ...clear all system memory displaying its progress on the screen The BIOS will then sign on any ISA or PCI option ROMs found on devices in the system If the F2 key was pressed during POST the ROM Utiliti...

Page 52: ...phase After the Power On Self Test POST process is complete control of the Plug and Play device configuration passes from the system BIOS to the system software The BIOS does however provide configura...

Page 53: ...o configure the hard drive types BOOT ORDER Used to specify boot device ordering PERIPHERALS Used to enable disable onboard I O devices USB CONFIG Used to configure USB Legacy Support MISC CONFIG Used...

Page 54: ...3F8 2F8 3E8 PCB Revision 1 0 BIOS Date 03 31 04 Memory Mode PC2100 266MHz DDR SDRAM with ECC PMC Slot 1 PCI X 66 MHz PMC Slot 2 PCI 33 MHz USB Devices 1 Keyboard 1 Mouse 1 Hub 1 Drive SYSTEM SUMMARY...

Page 55: ...e system time date and BIOS and system options SYSTEM SETUP CONFIGURATION UTILITY DATE TIME OPTIONS System Time 08 51 29 System Date Wed 03 31 2003 BIOS OPTIONS Quick Boot Disabled Summary Screen At B...

Page 56: ...abling this item causes Option ROM information to be displayed at signon AddOn ROM Display Delay When this item is enabled the BIOS will insert a brief pause after each option ROM signs on This is use...

Page 57: ...iversified Technology Incorporated IDE Config Descriptions Onboard PCI IDE Controller This item selects the configuration for the onboard parallel and serial IDE controllers P ATA Channel Selection En...

Page 58: ...Mode Supported Block Mode Not Supported PIO Mode 4 Async DMA Not Supported Ultra DMA Not Supported S M A R T Not Supported Type Auto LBA LARGE MODE Auto Block Multi Sector Transfer Mode Auto PIO MODE...

Page 59: ...DMA Mode S M A R T Displays device support for Self Monitoring Analysis and Reporting Technology This protocol allows detection of drive errors Type Selects the type of IDE device Type choices includ...

Page 60: ...ST to display a boot device menu This will over ride the boot order chosen in the CMOS Setup Utility and boot from the device selected BOOT ORDER CONFIGURATION SUMMARY BOOT DEVICE PRIORITY 1st Boot De...

Page 61: ...scending order beginning from the top of the list ATAPI CDROM Drives Boot from an IDE CDROM Hard Disk Devices Boot from hard disk drive The desired hard drive must be selected through Hard Disk Drives...

Page 62: ...Boot ROM Enabled I O PORT CONTROL ICH SIO Serial Port1 Address 3F8 ICH SIO Serial Port1 IRQ IRQ4 ICH SIO Serial Port1 Address 2F8 ICH SIO Serial Port2 IRQ IRQ3 IPMI Interface Port Address 3E8 IPMI In...

Page 63: ...default Remote Access This item allows serial console redirection to be enabled This allows all video output to be redirected through the serial port during the POST and DOS In addition input through...

Page 64: ...USB 2 0 Controller Enabled USB 2 0 Controller Mode FullSpeed Legacy USB Support Enabled USB Keyboard Legacy Support Enabled USB Mouse Legacy Support Enabled USB Storage Device Support Enabled USB MASS...

Page 65: ...s CD ROMs keyboards and mice can be accessed after POST has completed USB Keyboard Legacy Support When enabled this option allows any USB keyboard to be recognized as a standard input device by an Ope...

Page 66: ...K SETUP BOOT ORDER PERIPHERALS USB CONFIG MISC CONFIG EVENT LOGGING SECURITY VIRUS EXIT Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Copyright c 2004 Diversified Technology Incorporat...

Page 67: ...play devices Reset Configuration Data If set to Yes the plug play configuration is reset after leaving SETUP This option is automatically reset to No ACPI Power Settings ACPI 2 0 Support This item Ena...

Page 68: ...G EVENT LOGGING SECURITY VIRUS EXIT Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Copyright c 2004 Diversified Technology Incorporated Event Logging Descriptions View Event Log This it...

Page 69: ...SECURITY VIRUS EXIT Select Screen Enter Go to Sub Screen F1 General Help Esc Exit Copyright c 2004 Diversified Technology Incorporated Security Virus Descriptions Supervisor Password This item indica...

Page 70: ...Sub Screen F1 General Help Esc Exit Copyright c 2004 Diversified Technology Incorporated Exit Description Save Changes and Exit Exits SETUP and saves all changes to CMOS Discard Changes and Exit Exits...

Page 71: ...and the Plug and Play BIOS Specification Revision 1 0A B Assigns I O memory direct memory access DMA channels and IRQs from the system resource pool to the embedded PnP Super I O device C Does not sup...

Page 72: ...nsole via the serial link Keyboard inputs from both sources are considered valid and video is displayed to both outputs Optionally the system can be operated without a host keyboard or monitor attache...

Page 73: ...ST CODE 33 BIT values MSB to LSB 0011 0011 I I Upper Nibble Lower Nibble LEDS Status MSB to LSB Visible colors FFOO Off Off Orange Orange The following table is provided to show the most important POS...

Page 74: ...a monitor and confirm the board continues to count memory 2A 78 Check all PCI cards to verify they are fully seated in the backplane Remove and replace any newly added PCI cards OC Check keyboard 38...

Page 75: ...stics A 2 Absolute Maximum Ratings The values below are stress ratings only Do not operate the cPB 4612 at these maximums See the DC Operating Characteristics section in this appendix for operating co...

Page 76: ...e is a danger of explosion if the battery is incorrectly replaced or handled Do not disassemble or recharge the battery Do not dispose of the battery in fire When the battery is replaced the same type...

Page 77: ...l parameters In a CompactPCI enclosure with 0 8 inch spacing Mechanical dimensions are shown in the PCB Dimensions illustration and are outlined below PCB Dimensions 233 35 mm x 160 mm x 1 6 mm Board...

Page 78: ...67...

Page 79: ...Connector Function J15 CompactPCI Bus Connector 110 pin 2 mm x 2 mm female J11 CompactPCI Bus Connector 110 pin 2 mm x 2 mm female J8 CompactPCI Ethernet Connector 95 pin 2 mm x 2 mm female J2 Rear p...

Page 80: ...M1 Serial Port J4 USB Port J2 CompactPCI P5 J8 CompactPCI P3 J11 CompactPCI P2 J15 CompactPCI P1 U22 SO DIMM socket J14 2 5 HDD IDE connector if available DS1 BLUE LED J18 Header for CompactPCI Latch...

Page 81: ...70 Backplane Connectors Pin Locations 11 J1 1 15 25 J3 J5 1 19 1 22 1 22 J2 E D C B A E D C B A...

Page 82: ...CPCI_AD 23 D9 GND E9 CPCI_AD 22 A10 CPCI_AD 21 B10 GND C10 CPCI_VCC3 D10 CPCI_AD 20 E10 CPCI_AD 19 A11 CPCI_AD 18 B11 CPCI_AD 17 C11 CPCI_AD 16 D11 GND E11 CPCI_CBE 2 A12 NC key B12 NC key C12 NC key...

Page 83: ...ND C7 CPCI_VIO D7 CPCI_AD 58 E7 CPCI_AD 57 A8 CPCI_AD 56 B8 CPCI_AD 55 C8 CPCI_AD 54 D8 GND E8 CPCI_AD 53 A9 CPCI_AD 52 B9 GND C9 CPCI_VIO D9 CPCI_AD 51 E9 CPCI_AD 50 A10 CPCI_AD 49 B10 CPCI_AD 48 C10...

Page 84: ...E5 PIM 17 A6 PIM 60 B6 PIM 42 C6 PIM 41 D6 PIM 16 E6 PIM 15 A7 PIM 59 B7 PIM 40 C7 PIM 39 D7 PIM 14 E7 PIM 13 A8 PIM 58 B8 PIM 38 C8 PIM 37 D8 PIM 12 E8 PIM 11 A9 PIM 57 B9 PIM 36 C9 PIM 35 D9 PIM 10...

Page 85: ...X C9 GND D9 ENET_RX E9 ENET_RX A1 0 USBP2 B1 0 USBP2 C1 0 GND D1 0 USBP3 E1 0 USBP3 A1 1 VGA_VSYNC_ J5 B1 1 VGA_HSYNC_J 5 C1 1 VGA_BLUE_RT M_J5 D1 1 VGA_GREEN_RTM_ J5 E1 1 VGA_RED_RT M_J5 A1 2 VGA_DDC...

Page 86: ...ff 10 MB Green 100 MB Ethernet signals are directed out the front J1 port B 7 J4 Universal Serial Bus 0 connector J4 Port0 is a Universal Serial Bus USB Interface connector See the J4 Universal Serial...

Page 87: ...ide a complete 64 bit PCI interface See the following J6 PCI Mezzanine Connector Pin out J7 PCI Mezzanine Connector Pin out J9 PCI Mezzanine Connector Pin out and J10 PCI Mezzanine Connector Pin out t...

Page 88: ...6 37 GND 6 GND 38 STOP 7 GND 39 PERR 8 NC 40 GND 9 NC 41 VCC3 10 NC 42 SERR 11 BUSMODE2 43 CBE 1 12 VCC3 44 GND 13 PCIRST 45 PCI_AD 14 14 BUSMODE3 46 PCI_AD 13 15 VCC3 47 M66EN 16 BUSMODE4 48 PCI_AD 1...

Page 89: ...D 41 12 PCI_AD 62 44 GND 13 PCI_AD 61 45 GND 14 GND 46 PCI_AD 40 15 GND 47 PCI_AD 39 16 PCI_AD 60 48 PCI_AD 38 17 PCI_AD 59 49 PCI_AD 37 18 PCI_AD 58 50 GND 19 PCI_AD 57 51 GND 20 GND 52 PCI_AD 36 21...

Page 90: ...PIM 43 12 PIM 12 44 PIM 44 13 PIM 13 45 PIM 45 14 PIM 14 46 PIM 46 15 PIM 15 47 PIM 47 16 PIM 16 48 PIM 48 17 PIM 17 49 PIM 49 18 PIM 18 50 PIM 50 19 PIM 19 51 PIM 51 20 PIM 20 52 PIM 52 21 PIM 21 53...

Page 91: ...2_33 33 FRAME 2 12V 34 GND 3 GND 35 GND 4 INTA 36 IRDY 5 INTB 37 DEVSEL 6 INTC 38 VCC 7 BUSMODE1 39 GND 8 VCC 40 LOCK 9 INTD 41 SDONE 10 NC 42 SBO 11 GND 43 PAR 12 NC 44 GND 13 PCLKPMC 45 PWR_VIO_PMC...

Page 92: ...2 43 CBE 1 12 VCC3 44 GND 13 PCIRST 45 PCI_AD 14 14 BUSMODE3 46 PCI_AD 13 15 VCC3 47 GND 16 BUSMODE4 48 PCI_AD 10 17 PME 49 PCI_AD 8 18 GND 50 VCC3 19 PCI_AD 30 51 PCI_AD 7 20 PCI_AD 29 52 NC 21 GND 5...

Page 93: ...IDE_CONFIG_B 27 DREQ 3 IDE_CONFIG_C 28 GND 4 IDE_CONFIG_D 29 DIOW 5 NC 30 GND 6 NC 31 DIOR 7 RST 32 GND 8 GND 33 IORDY 9 DD 7 34 CABLE_SELECT 10 DD 8 35 DDACK 11 DD 6 36 GND 12 DD 9 37 IRQ 14 13 DD 5...

Page 94: ...83...

Page 95: ...s This appendix describes the thermal requirements for reliable operation of a cPB 4612 using the Mobile Pentium 4 processor M It covers basic thermal requirements and provides specifics about monitor...

Page 96: ...ient air temperature board temperature and processor core temperature Thermal Requirements External Ambient Air Temperature C Temperature Around the Board C Pentium M processor Core Temperature C 0 13...

Page 97: ...and verify that the core temperature does not exceed 65 C The processor core temperature must never exceed 100 C under any condition of ambient temperature or usage WARNING Temperatures over 100 C may...

Page 98: ...87...

Page 99: ...88 Appendix D D D Datasheet Reference This appendix provides links to datasheets standards and specifications for the technology designed into the cPB 4612...

Page 100: ...D 3 Intel 855GME Chipset For more information on the following cPB 4612 functions refer to the Intel 855GM 855GME Chipset Graphics and Memory Controller Hub datasheet Integrated Intel Extreme Graphics...

Page 101: ...sponsoring organization s Website at http www vita com D 6 Super I O Refer to the SMSC LPC47M192 Super I O with Hardware Monitoring Block datasheet for more information on the following cPB 4612 func...

Page 102: ...91...

Page 103: ...ment UL File E139737 EN IEC 60950 1 2001 Safety for Information Technology Equipment GR 63 CORE I2 2002 Designed to meet section 4 E 4 Electro magnetic Compatibility FCC Part 15 Subpart B 2003 Class A...

Page 104: ...wo conditions 1 This device may not cause harmful interference 2 This device must accept any interference received including interference that may cause undesired operation CAUTION If you make any mod...

Page 105: ...0 pin IDE connector and provides access to the following features on the rear panel Two USB 2 0 Ports Serial Communications on COM2 Video via standard CRT connector A PIM site that can be used in conj...

Page 106: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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