CPB4612 Configuration and Maintenance Guide
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2.8
Operating System Installation...........................................................................................................................17
3
CONFIGURATION .................................................................................................... 19
3.1
Switch Descriptions ............................................................................................................................................21
3.1.1
PB1 (Reset) ........................................................................................................................................................21
3.1.2
J16-1 (BKT-GND to GND) ...............................................................................................................................21
3.1.3
J16-2 (+12V to J5-pin D1). ................................................................................................................................22
3.1.4
J16-3 (+5V PMC I/O) ........................................................................................................................................22
3.1.5
J16-4 (IMPI Disable) .........................................................................................................................................22
3.1.6
J17-1 (Not Used)................................................................................................................................................22
3.1.7
J17-2 (CMOS Clear) ..........................................................................................................................................22
3.1.8
J17-3 (Disable Onboard Video) .........................................................................................................................23
3.1.9
J17-4 (Manufacture Test Mode) ........................................................................................................................23
3.1.10
J18 (Ejector Switch)...........................................................................................................................................23
4
RESET ...................................................................................................................... 24
4.1
Reset Types and Sources....................................................................................................................................25
4.1.1
Hard Reset Sources ............................................................................................................................................25
4.1.2
Soft Reset Sources .............................................................................................................................................25
4.1.3
Backend Power Down Sources ..........................................................................................................................25
4.1.4
NMI Sources ......................................................................................................................................................26
5
SYSTEM MONITORING AND CONTROL................................................................ 27
5.1
Monitoring and Control Functions...................................................................................................................28
Figure 5.1: Packet Structure ...........................................................................................................................................28
5.2
IPMB ...................................................................................................................................................................28
5.3
Field Replaceable Unit (FRU) Information......................................................................................................29
5.4
Sensors.................................................................................................................................................................29
5.5
Firmware Updates..............................................................................................................................................29
5.6
SMBus Address Map .........................................................................................................................................29
6
IDE CONTROLLER .................................................................................................. 30
6.1
Features of the IDE Controller .........................................................................................................................31
6.2
Disk Drive Support.............................................................................................................................................31
6.2.1
Primary IDE Channel.........................................................................................................................................31
6.2.2
Secondary IDE Channel.....................................................................................................................................31
6.3
IDE I/O Mapping ...............................................................................................................................................31
6.4
IDE Device Drivers.............................................................................................................................................31
7
WATCHDOG TIMER................................................................................................. 32
7.1
Watchdog Timer Overview ...............................................................................................................................33
7.2
PCI Configuration Registers .............................................................................................................................33
7.2.1
Base Address Register (10h)..............................................................................................................................33
7.2.2
WDT Configuration Register (60h) ...................................................................................................................34
7.2.3
WDT Lock Register (68h) .................................................................................................................................34
7.3
Memory Mapped Registers ...............................................................................................................................35
7.3.1
Preload Value 1 (BAR+00h)..............................................................................................................................35
