DIGITAL-LOGIC AG
FLATPANEL MANUAL V4.6
53 of 55
CGA-init table for LCD
SP14Q002
(320x240 1/4-VGA display)
Display
Signal
Board
Signal
Board
Signal
Texture
MSM486SL
J8
SM486PC-
EK
J51
1
D0
1
VL0
[LCDD0]
2
Serial row data
3
D2
3
VL2
[LCDD2]
4
Serial row data
4
D3
4
VL3
[LCDD3]
5
Serial row data
5
DISP OFF
20
VDD [LVDD]
(+5V)
1
Control display off
(0:off / 1:on)
6
FRAME
12
VL11
[LCD_FR]
13
The FLM signal indicates
the beginning of each
display cycle
7
NC
8
LOAD
10
VL9
[LCD_LC]
11
The CL1 latches the serial
data in shift register
9
CP
11
VL10
[LCD_SC]
12
Clock signal for shifting
the serial data
10
VDD (+ 5V)
20
VDD [LVDD]
(+5V)
1
Power supply logic CKT
11
VSS ( 0V)
17
GND
16
Ground
12
VEE (-22V)
1
9
LVEE [VEE]
(-2..-32V)
18
Power supply for LC
driving
13
V0 (-17V)
18
VXX (+5..-
32V)
19
Operating voltage for
LC driving
4
FGND
17
GND
16
Ground