DIGITAL-LOGIC AG
FLATPANEL MANUAL V4.6
52 of 55
6 D
ISPLAY ADAPTIONS FOR THE
ELAN400 CGA
CONTROLLER
6.1 4bit displays
CGA-init table for LCD
PC067AYE
(160x128 CGA display)
Display
Signal
Board
Signal
Board
Signal
Texture
MSM486SL
J8
SM486PC-
EK
J51
1
SP+
Speaker Anode
2
SP-
Speaker Cathode
3
VCC
20
VDD
1
[LVDD] (+5V) Power (3.3V)
4
VCC
20
VDD
1
[LVDD] (+5V) Enable 3.3V to the entire
LCD driver circuit
6
D2
3
VL2
4
[LCDD2]
Display Data D2
7
D1
2
VL1
3
[LCDD1]
Display Data D1
8
VSS
17
GND
16
Ground (0V)
9
D0
1
VL0
2
[LCDD0]
Display Data D0
10
D3
4
VL3
5
[LCDD3]
Display Data D3
11
VSS
17
GND
16
Ground (0V)
12
DP1(LP)
10
VL9
11
[LCD_LC]
Display Line Clock
13
VSS
17
GND
16
Ground (0V)
14
DP2(SCP)
11
VL10
12
[LCD_SC]
Display Panel Shift Data
Clock
15
FLM(FR)
12
VL11
13
[LCD_FR]
Display Frame Clock
16
M
9
VL8
10
[LCD_M]
Display AC Modulation
17
LVEE
19
LVEE
18
[VEE]
(-2..-32V)
Enable Bias when low
18
Serial Data Input to Bias
Supply to set volt
19
When low will put Bias
supply in sleep mode
20
VSS
17
GND
16
Ground (0V)
