Digital Equipment AXPpci 33, Design Manual

Page: 39 / 98

Physical Description
Table 2–20 shows the select frequencies supported for each processor.
Table 2–20 CPU Clock Frequency Select Jumper (J7)
Frequency
Alpha
Processor Pin 1–2
Jumper Pin 3–4
Jumper Pin 5–6
Jumper
66 MHz DECchip 21068 Out Out Out
100 MHz DECchip 21068A Out Out In
166 MHz DECchip 21066 Out In In
233 MHz
1
DECchip 21066A In Out In
1
Upgrade of 166 MHz boards to 233 MHz operation requires Digital Part Number
EBPXU–AA upgrade kit (factory installable only). For 233 MHz operation, the minimum
firmware revision is Version 1.3. See Section F.2 for details on how to obtain the latest
firmware.
See Section 2.2.4.5 for required SROM boot code selection.
2.2.4.3 Halt/Reset Select Jumper (J8)
The Halt/Reset select jumper (J8) is a 3-position (1 x 3) header that
determines if the system halts or resets when the Halt/Reset switch (see
connector J11) is closed, if installed. This jumper may be left off if the
Halt/Reset function is not required.
Table 2–21 lists the Halt/Reset select jumper pins.
Table 2–21 Halt/Reset Select Jumper (J8)
Reset Enable Halt Enable
1
PIn 1–2 PIn 2–3
1
Factory default
The factory setting for this jumper is always Halt Enable. The Reset
Enable position is for Digital manufacturing use only.
Note: Use of the Reset Enable function with Digital UNIX or Windows
NT may result in loss of data.
Table 2–22 lists the Halt/Reset operational settings.
Table 2–22 Halt/Reset Operational Settings
J8 Setting Windows NT Action Digital UNIX Action
Reset Enable (Pin 1–2) Reset (same as power up) Reset (same as power
up)
Halt Enable (Pin 2–3) Not supported Halt
2–21