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Award BIOS Setup Utility
3.1.3.1 DRAM Clock/Timing Control
Move the cursor to this field and press <Enter>. The following
screen will appear.
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Timing Control
The settings on the screen are for reference only. Your version may not be
identical to this one.
Item Help
Menu Level
↑↓→←
Move
F6:Fail-Safe Defaults
F7:Optimized Defaults
F1:General Help
Enter:Select
F5:Previous Values
+/-/PU/PD:Value
F10:Save
ESC:Exit
DRAM Timing Control
DRAM CAS Latency
RAS Active Time (tRAS)
RAS Precharge Time (tRP)
RAS to CAS Delay (tRCD)
DRAM Addr/Cmd Rate
By SPD
2.5T
6T
3T
3T
Auto
DRAM Timing Control
This field is used to select the timing of the DRAM.
By SPD
The EEPROM on a DIMM has SPD (Serial
Presence Detect) data str ucture that stores
information about the module such as the memory
type, memory size, memory speed, etc. When this
option is selected, the system will run according to
the information in the EEPROM. This option is the
default setting because it provides the most stable
condition for the system. The “DRAM CAS
Latency” to “RAS to CAS Delay (tRCD)” fields will
show the default settings by SPD.
Manual
If you want a better performance for your system
other than the one “by SPD”, select “Manual”. Then
select the best option in the “DRAM CAS
Latency” to “RAS to CAS Delay (tRCD)” fields.
X
X
X
X
