DFI G586OPC/E, User Manual

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G586OPC/E
17
Cache Configuration
The G586OPC system board can support either asyn-
chronous cache SRAM or synchronous (pipelined
burst) cache SRAM. Three cache sizes are supported:
256KB, 512KB and 1MB. 256KB is the default size.
Installing Asynchronous Cache SRAM
The SRAM sockets allow you to install either 32Kx8,
64Kx8 or 128Kx8 SRAM. Regardless of the amount of
cache memory installed, one 32Kx8 (U23) is needed for
tag RAM to store the cacheable addresses. The locations
of the SRAM sockets on the system board are shown on
the next page.
Note
Use only the 5V/3.3V mixed-voltage or pure 3.3V Data
SRAM chips if you are changing or upgrading the
asynchronous cache RAM of your system board. DO
NOT install the regular 5V cache chips in the Data
SRAM sockets; otherwise problems will occur because
they are not compatible. Regardless of the type of Data
SRAM used, install only 5V Tag SRAM on your system
board.
SRAM Socket