18
Cache Memory
The 586ITB system board can sup-
port 512KB pipeline burst, direct
map write-back cache SRAM. Your
system board comes with a 512KB
cache, which is the maximum
cache memory supported by the
system board, mounted at locations
U5 and U6. One SRAM is mounted
on location U7 for tag SRAM to
store the cacheable addresses.
Processor Installation
The 586ITB allows for easy installa-
tion of processors. Make sure all
jumpers are set correctly before ap-
plying power or you may damage the
processor or system board. Use a
needle-nosed plier to move the jump-
ers if necessary.
Jumper JP28 is used to set the exter-
nal system bus clock of your processor. Refer to the following pages for the
external system bus clock that corresponds to your processor and set this
jumper accordingly. The clock generator will determine the external bus
clock that must be sent to the processor through this setting.
Jumper JP1 and JP2 are used to set the frequency ratio of your processor.
Refer to the following pages for the frequency ratio that corresponds to your
processor and set these jumpers accordingly.
After setting these jumpers, an Intel processor will multiply the external bus
clock by the frequency ratio to become the internal clock speed. Internal
clock speed is the commonly used speed of Intel processors in the market
and is the actual operating clock of the processor (external bus clock x
frequency ratio = internal clock speed).