140
Pin
Pin Name
Symbol
I/O Type Det
Op
(Int.)
Pu/Pd
(Ext.)
Res P.OFF PURE
D
CEC
STBY Q.STBY
CEC +
Q STBY
Function
44 P50/CE
/CE/DSP BOOT O/I/I
C
-
-
SCPU3VPu Z
Z
O/L
-
-
-
/Rewriting boot startup "L" type configuration/DSP starts
rewriting "L" input
45 P47/(TXD7)/
SDA7
NC
O
C
-
-
DV3VPu
Z
O/L
O/L
-
-
-
Non
46 P46/(RXD7)/
SCL7
NC
O
C
-
-
DV3VPu
Z
O/L
O/L
-
-
-
Non
47 P45/(CLK7) HPD1
O
C
-
-
Pd
Z
Z
O/L
-
-
-
HD DET cotrol pin
48 P44
NC
O
C
-
-
SCPU3VPu Z
Z
O/L
O/L
O/L
O/L
Non
49 P43
NC
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
Non
50 P42
NC
O
-
Lv
-
SCPU3VPu Z
Z
O/L
O/L
O/L
O/L
Non
51 P41
CEC POWER
O
C
-
-
-
Z
Z
O/L O/H
O/L
O/H H: CEC STANDBY power supply ON ( H : ON)
52 P40
NC
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
Non
53 P37
HDMIR_RST
O
C
-
-
-
Z
Z
O/H O/H
O/L
O/H HDMI RECEIVER (ADV7840) for resetting
54 P36
1TX RST
O
C
-
-
SCPU3VPu Z
Z
O/H O/H
O/L
O/H HDMI TRANSMITTER1 (ADV7510) for resetting
55 P35
NC
O
C
-
-
SCPU3VPu Z
Z
O/L
O/L
O/L
O/L
Non
56 P34
Z1 SSIGDET
I
-
Lv
-
SCPU3VPu Z
Z
-
-
-
-
S signal detect input (Connected: H)
57 P33
VZ1INT
O
-
Lv
-
-
Z
Z
O/L
O/L
O/L
O/L
ANALOG VIDEO output DRIVER(NJM2566) control pin (L
: mute)
58 P32
SOCODECI
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
CODEC control pin : Communication cereal data
59 P31
CLKCODEC
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
CODEC control pin :Communication serial clock
60 VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
+3.3V
61 P30
CECODEC
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
CODEC control pin : Communication enable
62 VSS
VSS
-
-
-
-
-
-
-
-
-
-
-
GND
63 P27
CODECRST
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
CODEC control pin:Reset
64 P26
DIG VIDEO
POWER
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
GUI FPGA and its peripheral power control pin (PowerOn
: H)
65 P25/INT7
NC
O
-
Lv
-
CEC3VPu
Z
Z
-
-
-
-
Non
66 P24/INT6
1TX INT
I
-
Lv
-
CEC3VPu
Z
Z
-
-
-
-
HDMI OUT1 signal existence detection input (HDMI
TRANS1 ADV7510)
67 P23
HPD6
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
HD DET cotrol pin
68 P22
NC
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
Non
69 P21
NC
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
Non
70 P20
BD/AUX
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
ANALOG VIDEO output DRIVER(BH7868FS) control pin
(Pin S input it by BD "H" in "L").
71 P17/INT5
ADVINT1
I
-
E↓&L
-
-
Z
Z
-
-
-
-
HDMI RECEIVER(ADV7840)INT1 output
72 P16/INT4
ADVINT2
I
-
E↓&L
-
-
Z
Z
-
-
-
-
HDMI RECEIVER(ADV7840)INT2 output
73 P15/INT3
ADVINT3
I
-
E↓&L
-
-
Z
Z
-
-
-
-
HDMI RECEIVER(ADV7840)INT3 output
74 P14
(DSP3 ICS) /
SUBD CLK
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
Reserve (DSP3 control pin (ADSP-21367-333))/FPGA
rewriting control: DCLK
75 P13/TXD6
DSP MOSI
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
DSP control terminal (ADSP-21367-333): Data output
76 P12/RXD6
DSP MISO
I
-
Lv
-
-
Z
Z
-
-
-
-
DSP control terminal (ADSP-21367-333): Data input
77 P11/CLK6
DSPICLK
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
DSP control terminal (ADSP-21367-333): Clock output
78 P10
NC
O
-
Lv
-
-
Z
Z
-
-
-
-
Non
79 P07
PLD WRITE
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
PLD JTAGLINE ON/OFF control
80 P06
VSEL C1/TDO
O/I
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
GUI built-in VIDEO SW cotrol pin/PLD rewriting control
(JTAG)
81 P05
HPD3
O
C
-
-
-
Z
Z
O/L
-
-
-
HD DET cotrol pin
82 P04
(CPUCONT)
O
C
-
-
-
Z
Z
O/L
-
-
-
The preliminary terminal control is unnecessary (A.PLD
Control Bit).
83 P03
DIR INT
I
C
-
-
-
Z
Z
O/L
-
-
-
DIR cotrol pin(LC89058W-VF4A): DIR channel status
84 P02
NC
O
-
Lv
-
-
Z
Z
-
-
-
-
Non
85 P01
NC
O
C
-
-
-
Z
O/L
O/L
O/L
O/L
O/L
Non
86 P00
DIRRST
O
C
-
-
-
Z
O/L
O/L
O/L
O/L
O/L
DIR cotrol pin(LC89058W-VF4A): Reset
87 P107/(AN7) DSP1 RST
O
C
-
-
-
Z
Z
O/L
O/L
O/L
O/L
DSP(ADSP-21367-333) reset output terminal (Reset : L)
Summary of Contents for S-5BD
Page 54: ...54 ANALOG VIDEO OUTPUT SIGNAL Signal Color Bar 100 Composite S5BD Oscilloscope 75ohm Loard...
Page 135: ...135 ADAU1328BSTZ 8U 310035 IC103 66 AVR 2310CI 2310 890 AVC 2310 ADAU1328 IC301 HDMI B D...
Page 147: ...147 2 FL DISPLAY FLD 19 ST 02GINK FL851 PIN CONNECTION GRID ASSIGNMENT...
Page 148: ...148 ANODE CONNECTION...
