130
TAS5630PHD Terminal Functions
TERMINAL
NAME
PHD NO.
DKD NO.
FUNCTION
(1)
DESCRIPTION
AGND
8
10
P
Analog ground
BST_A
54
43
P
HS bootstrap supply (BST), external 0.033 uF capacitor to OUT_A required.
BST_B
41
34
P
HS bootstrap supply (BST), external 0.033 uF capacitor to OUT_B required.
BST_C
40
33
P
HS bootstrap supply (BST), external 0.033 uF capacitor to OUT_C required.
BST_D
27
24
P
HS bootstrap supply (BST), external 0.033 uF capacitor to OUT_D required.
/CLIP
18
-
O
Clipping warning; open drain; active low
C_STARTUP
3
5
O
Startup ramp requires a charging capacitor of
TBD
nF to AGND
FREQ_ADJ
12
14
I
PWM frame rate programming pin requires resistor to AGND
GND
7, 23, 24, 57, 58
9
P
Ground
GND_A
48, 49
38
P
Power ground for half-bridge A
GND_B
46, 47
37
P
Power ground for half-bridge B
GND_C
34, 35
31
P
Power ground for half-bridge C
GND_D
32, 33
29
P
Power ground for half-bridge D
GVDD_A
55
-
P
Gate drive voltage supply requires 0.1 uF capacitor to AGND
GVDD_B
56
-
P
Gate drive voltage supply requires 0.1 uF capacitor to AGND
GVDD_C
25
-
P
Gate drive voltage supply requires 0.1 uF capacitor to AGND
GVDD_D
26
-
P
Gate drive voltage supply requires 0.1 uF capacitor to AGND
GVDD_AB
-
44
P
Gate drive voltage supply requires 0.22 uF capacitor to AGND
GVDD_CD
-
23
P
Gate drive voltage supply requires 0.22 uF capacitor to AGND
INPUT_A
4
6
I
Input signal for half bridge A
INPUT_B
5
7
I
Input signal for half bridge B
INPUT_C
10
12
I
Input signal for half bridge C
INPUT_D
11
13
I
Input signal for half bridge D
M1
20
20
I
Mode selection
M2
21
21
I
Mode selection
M3
22
22
I
Mode selection
NC
59-62
-
-
No connect, pins may be grounded.
OC_ADJ
1
3
O
Analog over current programming pin requires resistor to ground.
13
15
I/O
Oscillaotor master/slave output/input.
OSC_IO-
14
16
I/O
Oscillaotor master/slave output/input.
/OTW
-
18
O
Overtemperature warning signal, open drain, active low.
/OTW1
16
-
O
Overtemperature warning signal, open drain, active low.
/OTW2
17
-
O
Overtemperature warning signal, open drain, active low.
OUT_A
52, 53
39
O
Output, half bridge A
OUT_B
44, 45
36
O
Output, half bridge B
OUT_C
36, 37
31
O
Output, half bridge C
OUT_D
28, 29
27
O
Output, half bridge D
PSU_REF
63
1
P
PSU Reference requires close decoupling of 330 pF to AGND
PVDD_A
50, 51
41, 42
P
Power supply input for half bridges A requires close decoupling of 0.01-uF capacitor
in parallel with 1.0-uF capacitor to GND_A
PVDD_B
42, 43
35
P
Power supply input for half bridges B requires close decoupling of 0.01-uF capacitor
in parallel with 1.0-uF capacitor to GND_B
PVDD_C
38, 39
32
P
Power supply input for half bridges C requires close decoupling of 0.01-uF capacitor
in parallel with 1.0-uF capacitor to GND_C
PVDD_D
30, 31
25, 26
P
Power supply input for half bridges D requires close decoupling of 0.01-uF capacitor
in parallel with 1.0-uF capacitor to GND_D
READY
19
19
O
Normal operation; open drain; active high
/RESET
2
4
I
Device reset Input; active low
/SD
15
17
O
Shutdown signal, open drain, active low
VDD
64
2
P
Power supply for digital voltage regulator requires a 47-uF capacitor in parallel with
a 0.1-uF capacitor to GND for decoupling.
VI_CM
6
8
O
Analog comparator reference node requires close decoupling of
47 uF to AGND
VREG
9
11
P
Digital regulator supply filter pin requires 0.1-uF capacitor to AGND
(1) I = input, O = output, P = power
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