TMP93CS40F (AU: IC301)
Name
Function
TMP93CS40F Terminal Function
Pin
No.
1
V REFL
A/D ref. GND
2
A Vss
←
A/D GND
3
A Vcc
←
AD +5V
4
_NMI
I
Not used (fixed to H)
5
P70/TI0
C15
O
C
Ed
L
L
Fixed to L (DSP ROM address cont. out bit 15, not used)
6
P71/TO1
C16
O
C
Ed
L
L
DSP program ROM address cont. out bit 16
7
P72/TO2
C17
O
C
Ed
L
L
DSP program ROM address cont. out bit 17
8
P73/TO3
ROM/RAM
O
C
Ed
L
L
ROM/RAM switching control terminal (L:ROM)
9
P80/INT4/TI4
_INTREQ OUT
I/O
C
Eu
E
↓
&L
Z
DSP request input and cont. output (L:Rq & cont.)
10
P81/INT5/TI5
B.DOWN
I
Eu
E
↑
&L
Z
Power down detect (H: Detected)
11
P82/TO4
O
C
L
L
12
P83/TO5
_REQ
O
C
Eu
H
L
MAIN-SUB CPU comm. control output (L: Comm. request from
sub)
13
P84/INT6/TI6
_ACK
I
Eu
E
↓
&L
MAIN-SUB CPU comm. control input (L: Ack. return from main)
14
P85/INT7/TI7
ERR
I
E
↑
&L
DIR control input terminal (LC89055Q)( H: ERR)
15
P86/TO6
I
Lv
Z
(GND)
16
P97/INT0
_CS
I
Ed
E
↑
&L
DIR control input terminal (LC89055Q), when CH status change
L
→
H
17
P90/TXD0
SI
O
C
MAIN-SUB CPU comm. control terminal (data output)
18
P91/RXD0
SO
I
MAIN-SUB CPU comm. control terminal (data input)
19
P92/_CTS0/SCLK0 CLK
I/O
C
MAIN-SUB CPU comm. control terminal (I2C clock in/output)
20
P93/TXD1
O
C
Z
L
21
P94/RXD1
O
C
Z
L
22
P95/SCLK1
O
C
Z
L
23
AM8/_16
←
Fixed to +5V
24
CLK
O
C
Eu
25
Vcc
←
+5V
26
Vss
I/O1
GND
27
X1
Xin
I
X
′
tal connection
28
X2
Xout
O
X
′
tal connection
29
_EA
←
Fixed to +5V
30
_RESET
RESET2_
I
Eu
Lv
L
Reset input (controlled by main CPU)
31
P96/XT1
A/D RESET
O
N
Eu
H
H
A/D control terminal (L: Reset)
32
P97/XT2
O
C
Ed
L
L
33
TEST1
←
I
Connected to TEST2
34
TEST2
←
I
Connected to TEST1
35
PA0
DINA
O
C
Ed
L
L
Digital input switching control output
36
PA1
DINB
O
C
Ed
L
L
Digital input switching control output
37
PA2
O
C
L
L
38
PA3
DINC
O
C
Ed
L
L
Digital input switching control output
39
PA4
DOUTA
O
C
Ed
L
L
Digital output switching control output
40
PA5
DOUTB
O
C
Ed
L
L
Digital output switching control output
Symbol
I/O
Type
Op
Det
Res
Init
Name
Function
Pin
No.
41
PA6
DEEMP
O
C
Ed
L
L
DAC de-emphasis filter cont. out terminal (H:ON)
42
PA7/SCOUT
96k-DAC
O
C
L
L
DAC control terminal (H: Sample frequency 96kHz)
43
ALE
O
C
L
L
(Address latch enable)
44
Vcc
+5V
45
P00/AD0
(AD0)
I/O
C
Z
L
(EPROM data in D0 / address out A0)
46
P01/AD1
(AD1))
I/O
C
Z
L
(EPROM data in D1 / address out A1)
47
P02/AD2
(AD2)
I/O
C
Z
L
(EPROM data in D2 / address out A2)
48
P03/AD3
(AD3)
I/O
C
Z
L
(EPROM data in D3 / address out A3)
49
P04/AD4
(AD4)
I/O
C
Z
L
(EPROM data in D4 / address out A4)
50
P05/AD5
(AD5)
I/O
C
Z
L
(EPROM data in D5 / address out A5)
51
P06/AD6
(AD6)
I/O
C
Z
L
(EPROM data in D6 / address out A6)
52
P07/AD7
(AD7)
I/O
C
Z
L
(EPROM data in D7 / address out A7)
53
P10/AD8/A8
(A8)
O
C
Z
L
(EPROM address out A8)
54
P11/AD9/A9
(A9)
O
C
Z
L
(EPROM address out A9)
55
P12/AD10/A10
(A10)
O
C
Z
L
(EPROM address out A10)
56
P13/AD11/A11
(A11)
O
C
Z
L
(EPROM address out A11)
57
P14/AD12/A12
(A12)
O
C
Z
L
(EPROM address out A12)
58
P15/AD13/A13
(A13)
O
C
Z
L
(EPROM address out A13)
59
P16/AD14/A14
(A14)
O
C
Z
L
(EPROM address out A14)
60
P17/AD15/A15
(A15)
O
C
Z
L
(EPROM address out A15)
61
_WDTOUT
←
O
C
Z
H
Watch dog output
62
Vss
←
GND
63
Vcc
←
+5V
64
P20/A0/A16
(A16)
O
C
Z
L
(EPROM address out A16)
65
P21/A1/A17
DIR CLK
O
C
Z
L
DIR control terminal (LC89055Q) control clock output
66
P22/A2/A18
DIR CE
O
C
Z
L
DIR control terminal (LC89055Q) control chip enable output
67
P23/A3/A19
DIR MOSI
O
C
Z
L
DIR control terminal (LC89055Q) control data output
68
P24/A4/A20
DIR MOSO
I
Lv
DIR control terminal (LC89055Q) control data input
69
P25/A5/A21
FGAIN
O
C
Ed
L
L
FRONT ch GAIN switching control output (H: SW=NO)
70
P26/A6/A22
DAC-RESET
O
C
Ed
L
H
DAC control terminal (L: Power down mode,
↑
(rising edge) Reset)
71
P27/A7/A23
SEL CK
O
C
Z
L
ADC/DIR data clock switching control terminal (L: ADC)
72
P30/_RD
(_RD)
O
C
Z
L
(Flash memory control terminal)
73
P31/_WR
(_WR)
O
C
Z
L
(Flash memory control terminal)
74
P32/_HWR
CSI
I
Lv
DIR control input terminal (L: PCM)
75
P33/_WAIT
ERR MUTE_
O
C
Ed
L
L
Pop noise preventive mute control output (L: Mute)
76
P34/_BUSRQ
I
Lv
Z
GND
77
P35/_BUSRQ
DIG.(AC3) MUTE
O
C
Ed
Z
L
Digital mute control output (L: AC-3 or DTS decode enable)
78
P36/_R/W
I
Lv
Z
GND
79
P37/_RAS
DIR RESET
O
C
Z
L
DIR control output (LC89055Q) (L: Reset)
80
P40/_CS0/_CAS0
O
C
Z
L
81
P41/_CS1/_CAS1
O
C
Z
L
82
P42/_CS2/_CAS2 (_CS0)
O
C
Z
L
(Flash memory control terminal)
83
P60/PG00
DSP. RESET
O
C
Z
L
DSP reset output terminal (L:Reset)
84
P61/PG01
I/02 SCD OUT
I
C
Lv
Z
DSP status data input terminal
85
P62/PG02
I/03 DSP. CS
O
Z
L
DSP chip select cont.output (L:Data out)
86
P63/PG03
I/04 DSP. CLK
O
C
Z
L
DSP data clock output terminal
87
P64/PG10
I/05 SCD IN
O
C
Z
L
DSP data output terminal
88
P65/PG11
I/06 4527_CE
O
C
Z
L
AD control terminal (AK4527), Chip enable output
89
P66/PG12
I/07 4527_CLK
O
C
Z
L
AD control terminal (AK4527), Data clock output
90
P67/PG13
I/08 4527_DIN
O
C
Z
L
AD control terminal (AK4527), Data output
91
Vss
←
GND
92
P50/AN0
INTTREQ IN
I
Eu
Lv
Z
93
P51/AN1
I
Eu
Lv
Z
94
P52/AN2
EMP
I
Lv
H: EMP on
95
P53/AN3
96K DET
I
Lv
96k signal detect input, H: 96k
96
P54/AN4
I
Eu
Lv
Z
97
P55/AN5
I
Eu
Lv
Z
98
P56/AN6
ACC ON/OFF
I
Eu
Lv
Z
99
P57/AN7
I
Eu
Lv
Z
100
V REFH
←
AD ref. +5V
Symbol
I/O
Type
Op
Det
Res
Init
7 5
7 6
1 0 0
1
2 5
2 6
5 0
5 1
16
AVR-2802/982
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Summary of Contents for AVR-2802
Page 62: ...SCHEMATIC DIAGRAMS 1 12 1 2 3 4 5 6 All manuals and user guides at all guides com ...
Page 63: ... 12V AVR 2802 982 6 7 8 9 10 11 A B C D All manuals and user guides at all guides com ...
Page 68: ... 2 5V SCHEMATIC DIAGRAMS 2 12 1 2 3 4 5 6 All manuals and user guides at all guides com ...
Page 69: ... 5V 5V 5V AVR 2802 982 6 7 8 9 10 11 A B C D All manuals and user guides at all guides com ...
Page 74: ...All manuals and user guides at all guides com ...
