Delta LD-100E-M22, Operating Manual

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Chapter 4 Communication Setting
LD-E Operation Manual
4-4
4.2 Communication protocol
ASCII Mode
Read Command Read Command Response Write Command Write Command Response
STX ’
：
’ STX ’
：
’ STX ’
：
’ STX ’
：
’
ADR 1 ‘0’ ADR 1 ‘0’ ADR 1 ‘0’ ADR 1 ‘0’
ADR 0 ‘1’ ADR 0 ‘1’ ADR 0 ‘1’ ADR 0 ‘1’
CMD 1 ‘0’ CMD 1 ‘0’ CMD 1 ‘0’ CMD 1 ‘0’
CMD 0 ‘3’ CMD 0 ‘3’ CMD 0 ‘6’ CMD 0 ‘6’
Starting data
address
‘1’
Number of data
(count by byte)
‘0’
Starting data
address
‘1’
Starting data
address
‘1’
‘0’ ‘4’ ‘0’ ‘0’
‘0’ Start address
data
1004H
‘D’ ‘0’ ‘0’
‘4’ ‘0’ ‘0’ ‘0’
Number of data
(word/Bit)
‘0’ ‘F’
Data content
‘0’
Data content
‘0’
‘0’ ‘5’ ‘0’ ‘0’
‘0’
Address data
1005H
‘0’ ‘0’ ‘0’
‘2’ ‘0’ ‘1’ ‘1’
LRC 1 ‘E’ ‘0’ LRC1 ‘E’ LRC1 ‘E’
LRC 0 ‘6’ ‘0’ LRC 0 ‘8’ LRC 0 ‘8’
END 1 CR LRC 1 ‘3’ END 1 CR END 1 CR
END 0 LF LRC 0 ‘3’ END 0 LF END 0 LF
END 1 CR
END 0 LF
LRC checksum:
LRC check is the added sum from “Address” to “Data content”. For example, 01H + 03H + 10H+ 04H + 00H + 02H = 1AH, then take the
complementary of 2, E6H.
RTU Mode
Read Command Read Command Response Write Command Write Command Response
ADR 01H ADR 01H ADR 01H ADR 01H
CMD 03H CMD 03H CMD 06H CMD 06H
Starting data
address
10H Number of data
(count by byte)
04H
Starting data
address
10H Starting data
address
10H
04H 00H 00H
Number of data
(word/Bit)
00H
Start address
data 1004H
D0H
Data content
00H
Data content
00H
02H F5H 01H 01H
CRC 1 81H
Address
data1005H
00H CRC 1 1DH CRC 1 1DH
CRC 0 0AH 00H CRC 0 0AH CRC 0 0AH
CRC 1 D2H
CRC 0 C1H
CRC (Cyclical Redundancy Check) is obtained by the following steps.
1. Load in a 16-bit register FFFFH as the CRC register.
2. Do an exclusive OR operation of the first byte of the data and low byte of CRC register, and place the operation result back to the CRC register.
3. Right shift the bits in the CRC register and fill the high bits with “0”. Check the removed lowest bit.
4. If the removed lowest bit is “0”, repeat step 3. Otherwise, do an exclusive OR operation of the CRC register and the value A001H and place the
operation result back to the CRC register.
5. Repeat step 3 and 4 until the 8 bits (1 byte) are all right shifted.
6. Repeat step 2 and 5 and calcualte all the bits to obtain CRC check.
Please be aware of the high/low byte transmission order in the CRC register.