General Memory Module Installation Guidelines
This system supports Flexible Memory Configuration, enabling the system to be configured and run in any valid chipset
architectural configuration. The following are the recommended guidelines for best performance:
•
UDIMMs and RDIMMs must not be mixed.
•
x4 and x8 DRAM based DIMMs can be mixed. For more information, see Mode-Specific Guidelines.
•
A maximum of two UDIMMs can be populated in a channel.
•
A maximum of two quad-rank RDIMMs can be populated in a channel.
•
A maximum of two single- or dual-rank RDIMMs can be populated in a channel.
•
One quad-rank RDIMM and one single- or dual-rank RDIMM can be populated per channel.
•
Populate DIMM sockets only if a processor is installed. For single-processor systems, sockets A1 to A6 are
available. For dual-processor systems, sockets A1 to A6 and sockets B1 to B6 are available.
•
Populate all sockets with white release tabs first and then black.
•
Populate the sockets by highest rank count in the following order - first in sockets with white release levers and
then black. For example, if you want to mix quad-rank and dual-rank DIMMs, populate quad-rank DIMMs in the
sockets with white release tabs and dual-rank DIMMs in the sockets with black release tabs.
•
In a dual-processor configuration, the memory configuration for each processor must be identical. For example,
if you populate socket A1 for processor 1, then populate socket B1 for processor 2, and so on.
•
Memory modules of different sizes can be mixed provided that other memory population rules are followed (for
example, 2 GB and 4 GB memory modules can be mixed).
•
Depending on mode-specific guidelines, populate two or three DIMMs per processor (one DIMM per channel)
at a time to maximize performance. For more information, see Mode-Specific Guidelines.
•
If memory modules with different speeds are installed, they will operate at the speed of the slowest installed
memory module(s) or slower depending on system DIMM configuration.
Mode-Specific Guidelines
Three memory channels are allocated to each processor. The allowable configurations depend on the memory mode
selected.
NOTE: x4 and x8 DRAM based DIMMs can be mixed providing support for (Reliability, Availability, and
Serviceability) RAS features. However, all guidelines for specific RAS features must be followed. x4 DRAM based
DIMMs retain Single Device Data Correction (SDDC) in either memory optimized (independent channel) or
Advanced ECC modes. x8 DRAM based DIMMs require Advanced ECC mode to gain SDDC.
The following sections provide additional slot population guidelines for each mode.
Advanced ECC (Lockstep)
Advanced ECC mode extends SDDC from x4 DRAM based DIMMs to both x4 and x8 DRAMs. This protects against single
DRAM chip failures during normal operation.
Memory installation guidelines:
•
Memory sockets A1, A4, B1, and B4 are disabled and do not supported Advanced ECC mode.
•
DIMMs must be installed in matched pairs — DIMMs installed in memory sockets (A2, B2) must match DIMMs
installed in memory sockets (A3, B3) and DIMMs installed in memory sockets (A5, B5) must match DIMMs
installed in memory sockets (A6, B6).
NOTE: Advanced ECC with mirroring is not supported.
42
Summary of Contents for PowerVault DX6104-CSN
Page 8: ...8 ...
Page 34: ...34 ...
Page 94: ...94 ...
Page 100: ...100 ...
Page 104: ...104 ...
Page 122: ...122 ...
