Table 39. Memory operating modes (continued)
Memory Operating Mode
Description
Single Rank Spare Mode
Single Rank Spare Mode
allocates one rank per channel as a
spare. If excessive correctable errors occur in a rank or
channel, while the operating system is running, they are
moved to the spare area to prevent errors from causing an
uncorrectable failure. Requires two or more ranks to be
populated in each channel.
Multi Rank Spare Mode
Multi Rank Spare Mode
allocates two ranks per channel as a
spare. If excessive correctable errors occur in a rank or
channel, while the operating system is running, they are
moved to the spare area to prevent errors from causing an
uncorrectable failure. Requires three or more ranks to be
populated in each channel.
With single rank memory sparing enabled, the system
memory available to the operating system is reduced by one
rank per channel.
For example, in a
dual-processor configuration with 24x 16 GB dual-rank
memory
modules, the available system memory is: 3/4 (ranks/channel)
×
24 (memory modules) × 16 GB = 288 GB, and not 24 (memory
modules) × 16 GB = 384 GB. For multi rank sparing, the
multiplier changes to 1/2 (ranks/channel).
NOTE:
To use memory sparing, this feature must be
enabled in the BIOS menu of System Setup.
NOTE:
Memory sparing does not offer protection against
a multi-bit uncorrectable error.
Dell Fault Resilient Mode
The
Dell Fault Resilient Mode
if enabled, the BIOS creates
an area of memory that is fault resilient. This mode can be
used by an OS that supports the feature to load critical
applications or enables the OS kernel to maximize system
availability.
NOTE:
This feature is only supported in Gold and Platinum
Intel processors.
NOTE:
Memory configuration has to be of same size
DIMM, speed, and rank.
Optimizer Mode
This mode supports Single Device Data Correction (SDDC) only for memory modules that use x4 device width. It does not
impose any specific slot population requirements.
●
Dual processor: Populate the slots in round robin sequence starting with processor 1.
NOTE:
Processor 1 and processor 2 population should match.
Table 40. Memory population rules
Processor
Configuration
Memory population
Memory population information
Single processor
Optimizer (Independent
channel) population order
1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12
●
DIMMs must be populated in the order
specified.
●
Odd number of DIMM population is allowed
114
Installing and removing system components
Summary of Contents for 5WC10
Page 21: ...Figure 16 Configuration and layout Dell EMC PowerEdge T640 overview 21 ...
Page 22: ...Figure 17 Electrical overview 22 Dell EMC PowerEdge T640 overview ...
Page 23: ...Figure 18 Memory information Dell EMC PowerEdge T640 overview 23 ...
Page 24: ...Figure 19 System tasks 24 Dell EMC PowerEdge T640 overview ...
