B E L K Q u i c k S t a r t G u i d e
v . 1 . 0 . 9
Check that the patch is correctly applied to the source code
and click on
Finish
●
with the same procedure, apply the patches to fix DDR3 CKE
deassertion time (see also
http://www.xilinx.com/support/answers/65145.html
):
apply
<bora_repo>/patch/AR65145_ps7_init_c.patch
on
ps7_init.c
under
bora_wrapper_hw_platform_0
apply
<bora_repo>/patch/AR65145_ps7_init_tcl.patch
on
ps7_init.tcl
under
bora_wrapper_hw_platform_0
●
the FSBL (ELF file) is built automatically
●
create the binary from the FSBL ELF chosing one of the
following options:
(this step is board dependent) manually launch the
command:
arm-xilinx-eabi-objcopy -v -O binary
$PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/b
ora_FSBL.elf
$PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/b
ora_FSBL.bin
(this step is board dependent) configure the automatic
binary generation on project build. In Project Explorer,
right-click on “bora_FSBL” project and select
C/C++ Build
Settings
and add the command
arm-xilinx-eabi-objcopy
-v -O binary ${ProjName}.elf ${ProjName}.bin
on
Post-build steps
●
create the BOOT.bin image (single file including FSBL, FPGA
and U-boot for uSD boot:
select the bora_FSBL project in
Project Explorer
click on
Xilinx Tools -> Create Zynq Boot Image
●
if the project is correctly configured, the tool builds
automatically all the component listed in the form, so just add
U-Boot to the list.
●
otherwise, select
Create new BIF
file and set the output path
and in
Boot image partitions
add the following files:
bora_FSBL.elf
, which can be found in the project Debug
directory. N.B. check that the Partition Type for FSBL is
March, 2016
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