B E L K Q u i c k S t a r t G u i d e
v . 1 . 0 . 9
the
Flow Navigator
●
insert
bora
(or
borax
) as
Design name
and click OK
●
this creates a new block design. From the Diagram
tab, add a new IP:
click the
Add IP
side button, or
click
Add IP
on the upper suggestions bar
●
double click on
ZYNQ7 Processing System
●
this adds the IP that models the PL component of
Zynq. Launch
Run Block Automation
from the
upper suggestions bar
●
check that
Apply Board Preset
is selected and click
OK
●
this applies the default settings for BORA/BORAX and
creates the I/O ports for the DDR and MIO pins and
for the UART_0 and CAN_0 interfaces
●
manually connect the
FCLK_CLK0
signal to
M_AXI_GP0_ACLK
and save the block design
●
from the sources tab, select the BORA/BORAX block
design (
bora.bd
for BORA,
borax.bd
for BORAX) as
Design Sources
and from the context menu select
Create HDL Wrapper
●
on the next window, select
Copy generated wrapper
to allow user edits and click OK
●
this creates the Verilog file (
bora_wrapper.v
for
BORA,
borax_wrapper.v
for BORAX). If this file is not
automatically included in the project, add it using the
Add sources
option
select
Add or create design sources
and click
Next
select the
bora_wrapper.v
file from the
<prj_name>.srcs/sources_1/bd/bora/hdl/
directory
●
select
Add sources
and click on
Add or create
constraints
●
select the
bora_pinout.xdc
and
bora_timings.xdc
March, 2016
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