9: Processor Board
PRC1099A-MS
9-5
9.1.13
Analog Converter System
The analog converter system consists of the analog-to-digital converter
(ADC) chip U6 and the analog multiplexer chip U7.
The analog multiplexer selects the proper input into the ADC chip. The ADC
chip has a 256-position precision resistor array that lets it determine the input
voltage down to a resolution of 20 mV. The analog converter system allows
precise monitoring of the battery voltage, ALC line, AGC line, handset
voltage, 8 VDC, receive 8 VDC, and transmit 8 VDC.
9.1.14
Audio Buffers
Op amp U19 buffers the transmit and receive audio signals to and from the
optional ALE card.
9.1.15
ALE Switch
FET switch U21 switches the power to the optional ALE card on and off.
9.1.16
Program Operation
Most of the time, the processor is in standby mode waiting for a command
from any of the inputs. When a control input changes, the state-change
detector signals the processor to switch to active mode. The processor then
polls all the inputs through the input demultiplexer to find out which input
triggered the interrupt.
Upon determining the correct input, the processor executes the proper
instructions to perform the command determined by the specific input. For
example, a change in the channel switch line would wake up the processor,
that then retrieves the new channel frequency data stored in RAM. The new
channel data is then sent to the synthesizer, antenna tuner, and harmonic filter
through the control bus, and the Display board data is sent through the display
bus.
The input to any of the UART’s and the rest of the interrupt sources is very
similar, except all the interrupt circuitry is internal to the 68302 chip.
9.1.17
Control Bus
The control bus basically consists of three signals: clock, data, and select. The
processor places the first data bit on the data line at the SPTXD pin. It then
toggles the clock line (SPCLK) twice, so that the data is shifted into the
selected shift register. This is repeated until all the data in the data stream is
shifted out. 3-to-8 Demultiplexer U10 chooses the desired select line by
putting the proper address on PA2 through PA4. The processor toggles the
select line twice to latch the shifted data into the desired register.
