8: Synthesizer Board
8-2
PRC1099A-MS
8.1.1
Reference Oscillator
Temperature-compensated crystal oscillator (TCXO) Y1 provides a 100 MHz
reference frequency for the DDS synthesizer with a standard frequency
tolerance of 1 ppm over temperature. It includes a fine adjustment to allow
centering of the oscillator’s frequency at the time of synthesizer calibration.
The complete frequency determination of the entire transceiver is locked to
this reference, giving the output frequency a stability equal to that of the
TCXO. An in-line 1:1 balun transformer converts the single-ended oscillator
output to a balanced input for the DDS.
8.1.2
Direct Digital Synthesizer (DDS)
The Direct Digital Synthesizer (DDS) generates two local oscillator
frequencies: LO1 and LO2, that are routed to the Mixer board where they
either up-convert or down-convert the transmit or receive frequency. The DDS
receives channel frequency data from the processor over SPI serial data lines.
The BFO (beat frequency oscillator) output (1647 or 1650 kHz) is routed to
the Audio/Filter board where it is modulated by the transmit audio. The BFO
is also used to demodulate the receive signal leaving just the receive audio.
The 4-channel DDS produces all the local oscillator outputs, including the
BFO. The BFO is generated in channel 2, the first LO (76.6 to 105 MHz) is
generated in channel 1, and the second LO (73.35 MHz) is generated by
channel 0. The fourth channel is unused.
The DDS operates all three local oscillators at the appropriate frequency. The
device is tuned by inputting a 32-bit digital tuning word expressed by:
8.1.3
PLL/Tracking Filter
The first LO uses a phase-locked loop (PLL) circuit that filters the output of
the DDS first local oscillator (LO1) to remove any wide-band spurious signals
and noise. The loop filter of the PLL is composed of U17, R101, R102 and
R133 together with C121, C123, C124, and C125. The output of U17 controls
the frequency of VCO U16.
The PLL circuit also tracks the LO1 output frequency exactly using low-noise
VCO U16 so there is no additional division noise commonly associated with
phase locked loops.
F
o
= (FTW)(Fs)/2
32
where:
F
o
= DDS output frequency
0<= FTW <= 2
31
FTW = Frequency tuning word
Fs = System clock rate
