Datex-Ohmeda CAPNOMAC ULTIMA, Service Manual

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DATEX CAPNOMAC ULTIMA
TM
SERVICE MANUAL 5-31
5.7 Video control board
Block diagram
Parts layout and timing diagram
Schematic diagram Figure 5.17
Figure 5.18
Figure 5.19
Principle of operation
The video control board (see the block diagram) is based on an LSI
graphics display processor
GDP (D4), which accepts
commands
from the CPU via the system bus and converts them to operations
on a bit image in the
video
RAM memory. The video RAM is then
continuously scanned by addressing logic and a video shift register
to produce a 24 MHz dot stream that forms the screen image. The
display processor adds the synchronization information, which is
separated into vertical (50 Hz) and horizontal (15 kHz) components
before being sent to the CRT unit. The signals are also combined
into a composite video signal, which is output to the rear panel.
May 2nd, 1991/1