Data Translation DT9840 Series, User Manual

Page: 56 / 130

Chapter 2
56
Analog Input Subsystem
On the DT9841E, the A/D subsystem consists of two A/D converters that are simultaneously
clocked. On all other DT9840 Series modules, the A/D subsystem consists of eight A/D
converters that are simultaneously clocked.
On the DT9841, DT9841E and DT9841-VIB, the major components of this subsystem are the
Delta-Sigma A/D converters and the sample clock oscillator. The Delta-Sigma converters
remove anti-aliasing on the analog inputs and outputs. The sample clock (MCLK) determines
the sampling rate at which all analog input channels, all digital input channels, and all
counter/timer channels are simultaneously sampled. The minimum clock rate is 2
kSamples/s once the subsystems have been configured and started. For lower sampling rates,
the DSP chip needs to be set up to discard unneeded samples using a filtering algorithm. The
maximum clock rate is 100 kSamples/s. A digital filter is used to scale with the sampling rate.
On the DT9842/2 and DT9842/8, the major components of this subsystem are the successive
approximation A/D converters and the sample clock oscillator. A 32-bit Clock Divider
register (address 0xB0000008) controls the sampling rate of both the A/D and D/A
converters. The value of this register divides the onboard 18 MHz sample clock oscillator. The
default value of this register at system reset (and the maximum value that this register should
be set to) is 180 (0xB4); this value results in a maximum sampling rate of 100 kSamples/s.
Using bit 30 of the Hardware and Control Status register, described in Table 5 on page 47 , you
can select either an internal or external clock source. MCLK is programmed using bits 28 and
29 of the Calibration and Setup register, described in
Table 6 on page 51 . When the external
clock is selected, conversion begin on the high-to-low transition after a rising edge of the
internal CAL signal.
On the DT9841 and DT9841E, any or all of the analog input low signals can be terminated with
a 1 k
Ω
bias return resistor to the isolated analog common. Bits 20, 26, and 27 of the Calibration
and Setup register, described in Table 6 on page 51 , control the termination multiplexer. The
termination function can be initiated independently from all other functions.
To initialize the A/D subsystem on the DT9841, DT9841E, or DT9841-VIB, serial port 0 (TI
PCM1804) is used in SPI mode, and the A/Ds are set up for control port mode. Oversampling
mode is 64x with a data width of 24 bits and twos complement data encoding; high-pass
filtering is defeated. Note that this serial port is also used to synchronize up to three slave
modules using an external clock. All connected modules receive the same setup information
for the A/D and D/A subsystems over the Scalable Bus (see
page 72 for more information on
the Scalable Bus). Note that the rising edge of the CAL signal must be timed with the falling
edge of the MCLK signal for simultaneous sample-and-hold operations. This is synchronized
in the Spartan chip on the master module.
No initialization is required for the A/D subsystem on the DT9842/2 and DT9842/8 modules.
The A/D converters are wired for the desired operation.
A/D conversions start on an internal (software) trigger or external trigger. An internal trigger
is initiated by a software command. An external trigger is initiated by a low-to-high transition
on the external TTL trigger input to the module; this trigger asserts EXT_INT4 for processing.
Scanning is continuous through all A/D channels, digital inputs, and counter/timers. The
DSP program can discard unneeded data.