Data Translation DT9840 Series, User Manual

Page: 72 / 130

Chapter 2
72
Scalable Bus
Note: The Scalable Bus is not supported by DT9841E modules.
Two 50-pin connectors (J12 and J13) on the DT9840 Series module provide a Scalable Bus for
connecting modules together. By plugging EP342 cables from one module to another, you can
connect up to three "slave" modules to a DT9840 Series "master" module. The first module
(usually the master) and the final module (usually a slave) in the chain must be terminated in
software with 100 ohms. Bit 25 of the Calibration and Setup register, described in
Table 6 on
page 51 , controls the 100 ohm termination resistors.
The Scalable Bus connector is set up for intermodule communication at speeds up to 50
MBytes/s (note however, that the maximum rate in software is 11.3 MBytes/s). The negative
strobe pulse must be 12 ns minimum with the data valid for 10 ns before the rising edge. The
hold time is 0 ns. The data can be clocked every 40 ns.
The slave module is responsible for requesting to receive data from the master or requesting
to send data to the master. Only one slave can request the Scalable Bus at any one time.
When it requests a transfer, the slave module asserts interrupt EXT_INT4. The master module
then reads each slave at a time to determine which module asserted the interrupt line. The
requesting slave module determines the size of the data that is transferred. The module that is
being written to indicates when the transfer operation is complete.
When the Scalable Bus is idle, the master module drives the data bus; it does not need to drive
the Request line.
The following registers are used to control the operation of the Scalable Bus:
• SB Control register, described in Table 16 on page 72
• SB Transfer Control register, described in Table 17 on page 73
• SB Transfer Status register, desribed in Table 18 on page 74
Table 16: SB Control Register (Address 0xB0014000)
Bit Register Name Register Description Type
0 to 2
a
Module Address These are the slave addresses for modules 1 through 3. For
slaves, set these bits to a unique address for the module. For
the master, set these bits to 000. R/W
3 Master Module 1 = The module is the master (determined at initial setup).
0 = The module is a slave. R/W
4 - 7 Reserved – R
8 FIFO Half Full 1 = The FIFO on the Scalable Bus is half full; this asserts
interrupt EXT_INT7 for transfers to memory.
0 = The FIFO on the Scalable Bus is not half full.
R