Data Translation DT9824, User Manual, Page: 83 / 102

Specifications
83
Offset drift versus temperature
≤
600Hz:
> 600Hz:
50 nV/
°
C
150 nV/
°
C
Offset drift versus time 25 nV/1000 hours typical
Gain drift versus temperature ±10 ppm/
°
C
Gain drift versus time 10 ppm/1000 hours typical
Input impedance
Power off:
Power on:
3 k
Ω
10 M
Ω
// 3 k
Ω
in series with 4700 pF
Input bias current
≤
±1 nA
Input noise (@10 Hz sample rate; gain of 1) 3.6
μ
V rms = 23.6
μ
V pp or < 1.5 ppm
(see Figure 17 on page 84 )
System noise See Table 23 and Figure 18 on page 85
Analog input filter 10 kHz
Common mode rejection @ 10 Hz > –150 dB @ 50 Hz and 60 Hz
Common mode voltage ±500 V maximum (operational)
Maximum input voltage ±40 V maximum (protection)
Channel-to-channel offset ±10
μ
V
Effective number of bits (ENOB)
@10 Hz with a 1 Hz, ±9.9 V sine wave input
21 bits typical
Channel crosstalk
–
150 dB @ 1 kHz
Input coupling DC
Isolation voltage ±500 V to computer ground
Channel-to-channel isolation ±500 V
ESD protection
Arc:
Contact: 8 kV
4 kV
Internal reference 1.25 V ±0.001 V
–
3 dB point (low pass)
a
Sample rate less than or equal to 600 Samples/s
Sample greater than 600 Samples/s f
−
3 dB = 0.24 x fADC
f
−
3 dB = 0.23 x fADC
Internal clock ±100 ppm maximum (typical initial ±25 ppm)
b
Warm-up time 1 hour
a. Refer to page 85 for more information about the frequency response, input bandwidth, and correction factors.
b. This clock is derived from the crystal oscillator. The specification includes initial tolerance, power supply variations,
temperature drift, and 1 year stability.
Table 22: A/D Subsystem Specifications (cont.)
Feature DT9824 Specifications