Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 157 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 157
SPI
18.3.3 SPIS Timing
Enable/Disable Operation. As soon as the block is config-
ured for SPI Slave and before enabling, the MISO output is
set to idle at logic 1. The Enable bit must be set and the SS_
asserted (either driven externally or forced by firmware pro-
gramming) for the block to output data. When enabled, the
primary output is the MSb or LSb of the Shift register,
depending on the LSb First configuration in bit 7 of the Con-
trol register. The auxiliary output of the SPIS is always
forced into tristate.
Since the SPIS has no internal clock, it must be enabled
with setup time to any external master supplying the clock.
Setup time is also required for a TX Buffer register write
before the first edge of the clock or the first falling edge of
SS_, depending on the mode. This setup time must be
assured through the protocol and an understanding of the
timing between the master and slave in a system.
When the block is disabled, the MISO output reverts to its
idle 1 state. All internal state is reset (including CR0 status)
to its configuration-specific reset state, except for DR0,
DR1, and DR2, which are unaffected.
Normal Operation. Typical timing for an SPIS transfer is
shown in Figure 18-9 and Figure 18-10 . If the SPIS is prima-
rily being used as a receiver, the RX Reg Full (polling only)
or SPI Complete (polling or interrupt) status may be used to
determine when a byte has been received. In this way, the
SPIS operates identically with the SPIM. However, there are
two main areas in which the SPIS operates differently: 1)
SPIS behavior related to the SS_ signal, and 2) TX data
queuing (loading the TX Buffer register).
Figure 18-9. Typical SPIS Timing in Modes 0 and 1
SCLK (Internal)
TX REG EMPTY
D7
MISO
D6 D5 D2 D1 D0
User writes first byte to the
TX Buffer register in
advance of transfer.
At the falling edge of SS_, MISO
transitions from an IDLE (high)
to output the first bit of data.
User writes the next byte
to the TX Buffer register.
SCLK (MODE 0)
Last bit of received data is valid
on this edge and is latched into
the RX Buffer register.
SCLK (MODE 1)
SS_
RX REG FULL
First input
bit is
latched.
First
Shift.
D7 D6 D7
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