Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 158 / 308

158 PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SPI
Figure 18-10. Typical SPIS Timing in Modes 2 and 3
Slave Select (SS_, Active Low).
Slave Select must be
asserted to enable the SPIS for receive and transmit. There
are two ways to do this:
■
Drive the auxiliary input from a pin (selected by the Aux
I/O Select bits in the output register). This gives the SPI
master control of the slave selection in a multi-slave
environment.
■
SS_ may be controlled in firmware with register writes to
the output register. When Aux I/O Enable = 1, Aux I/O
Select bit 0 becomes the SS_ input. This allows the user
to save an input pin in single-slave environments.
When SS_ is negated (whether from an external or internal
source), the SPIS state machine is reset and the MISO out-
put is forced to idle at logic 1. In addition, the SPIS ignores
any incoming MOSI/SCLK input from the master.
Status Generation and Interrupts. There are four status
bits in the SPIS block: TX Reg Empty, RX Reg Full, SPI
Complete, and Overrun. The timing of these status bits are
identical to the SPIM, with the exception of TX Reg Empty,
which is covered in the section on TX data queuing.
Status Clear On Read.
Refer to the same subsection in
SPIM Timing on page 152 .
TX Data Queuing. Most SPI applications call for data to be
sent back from the slave to the master. Writing firmware to
accomplish this requires an understanding of how the Shift
register is loaded from the TX Buffer register.
All modes use the following mechanism: 1) If there is no
transfer in progress, 2) if the shifter is empty, and 3) if data is
available in the TX Buffer register, the byte is loaded into the
shifter.
The only difference between the modes is that the definition
of “transfer in progress” is slightly different between modes 0
and 1, and modes 2 and 3.
SCLK (Internal)
TX REG EMPTY
D7 MISO D6 D5 D2 D1 D0 D7
User writes the first
byte to the TX Buffer
register.
Shifter is loaded with
first byte (by leading
edge of the SCLK).
User writes the next
byte to the TX Buffer
register.
SCLK (MODE 2)
Shifter is
loaded with
the next byte.
Last bit of received data is valid
on this edge and is latched into
the RX Buffer register.
SCLK (MODE 3)
RX REG FULL
First
input bit
latched.
First
Shift.
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