Cypress CY8CKIT-043, Manual

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CY8CKIT-043 PSoC® 4 M-Series Prototyping Kit Guide, Doc. #: 001-97606 Rev. ** 26
Hardware
4.2.5.2 Functionality of J7 and J3 Headers (PSoC 4200M to KitProg)
The KitProg and target boards each contain a 1×5-pin header. These headers provide a physical
connection between the two devices. Specifically, the connection includes the SWD interface,
required to program/debug the target PSoC 4200M device, power, ground, and reset.
Table 4-1. J1 Header Pin Details Table 4-2. J2 Header Pin Details
PSoC 4 M-Series Prototyping Kit GPIO
Pin Signal Description
J1_01 /XRES GPIO
J1_02 P5[0] GPIO
J1_03 P5[1] GPIO
J1_04 P5[2] GPIO
J1_05 P5[3] GPIO
J1_06 P5[5] GPIO
J1_07 P1[0] GPIO
J1_08 P1[1] GPIO
J1_09 P1[2] GPIO
J1_10 P1[3] GPIO
J1_11 P1[4] GPIO
J1_12 P1[5] GPIO
J1_13 P1[6] GPIO/LED (LED1)
J1_14 P1[7] GPIO/SAR BYPASS
J1_15 P2[0] GPIO
J1_16 P2[1] GPIO
J1_17 P2[2] GPIO
J1_18 P2[3] GPIO
J1_19 P2[4] GPIO
J1_20 P2[5] GPIO
J1_21 P2[6] GPIO
J1_22 P2[7] GPIO
J1_23 P6[0] GPIO
J1_24 P6[1] GPIO
J1_25 P6[2] GPIO
J1_26 P6[4] GPIO
J1_27 P6[5] GPIO
J1_28 GND Ground
J1_29 VDDIO Power
PSoC 4 M-Series Prototyping Kit GPIO
Pin Signal Description
J2_01 VDDD Power
J2_02 GND Ground
J2_03 P0[7] GPIO/SW (SW1)
J2_04 P0[6] GPIO
J2_05 P0[5] GPIO/XTAL_OUT
J2_06 P0[4] GPIO/XTAL_IN
J2_07 P0[3] GPIO
J2_08 P0[2] GPIO
J2_09 P0[1] GPIO
J2_10 P0[0] GPIO
J2_11 P7[1] GPIO/->UART_RX
J2_12 P7[0] GPIO/<-UART_TX
J2_13 P4[6] GPIO
J2_14 P4[5] GPIO
J2_15 P4[4] GPIO
J2_16 P4[3] GPIO/CTANK
J2_17 P4[2] GPIO/CMOD
J2_18 P4[1] GPIO/I2C_SDA
J2_19 P4[0] GPIO/I2C_SCL
J2_20 P3[7] GPIO
J2_21 P3[6] GPIO
J2_22 P3[5] GPIO
J2_23 P3[4] GPIO
J2_24 P3[3] GPIO/SWDCLK
J2_25 P3[2] GPIO/SWDIO
J2_26 P3[1] GPIO/->BLE_RX
J2_27 P3[0] GPIO/<-BLE_TX
J2_28 VDDA Power
J2_29 GND Ground