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CY7C68013

Document #: 38-08012 Rev. *A

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PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
VCC
DPLUS
DMINUS
GND
VCC
GND
IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3

56

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PD4/FD12
PD3/FD11
PD2/FD10

PD1/FD9
PD0/FD8

*WAKEUP

VCC

RESET#

GND

PA7/*FLAGD/SLCS#

PA6/PKTEND

PA5/FIFOADR1
PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#
PA0/INT0#

VCC

CTL2/*FLAGC

CTL1/*FLAGB
CTL0/*FLAGA

GND

VCC

GND

PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4

CY7C68013
56-pin SSOP

Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment

* denotes programmable polarity

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Summary of Contents for CY7C68013

Page 1: ...ss Semiconductor Corporation 3901 North First Street San Jose CA 95134 408 943 2600 Document 38 08012 Rev A Revised January 15 2002 68013 CY7C68013 EZ USB FX2 USB Microcontroller High Speed USB Periph...

Page 2: ...Y7C68013 Pin Descriptions 23 5 0 REGISTER SUMMARY 30 6 0 ABSOLUTE MAXIMUM RATINGS 36 7 0 OPERATING CONDITIONS 36 8 0 DC CHARACTERISTICS 36 9 0 AC ELECTRICAL CHARACTERISTICS 37 9 1 USB Transceiver 37 9...

Page 3: ...ous Read Timing Diagram 12 40 Figure 9 6 Slave FIFO Asynchronous Read Timing Diagram 12 41 Figure 9 7 Slave FIFO Synchronous Write Timing Diagram 12 41 Figure 9 8 Slave FIFO Asynchronous Write Timing...

Page 4: ...FO Synchronous Read Parameters with Internally Sourced IFCLK 14 40 Table 9 7 Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK 14 40 Table 9 8 Slave FIFO Asynchronous Read Parameter...

Page 5: ...TQFP and 128 TQFP Single chip integrated USB 2 0 Transceiver Serial Interface Engine SIE and Enhanced 8051 Microprocessor Software 8051 runs from internal RAM which is Downloaded via USB or Loaded fr...

Page 6: ...6 pin SSOP 2 0 Applications DSL modems ATA interface Memory card readers Legacy conversion devices Cameras Scanners Home PNA Wireless LAN MP3 players Networking The Reference Designs section of the cy...

Page 7: ...source that generates overflow pulses at the appropriate time The internal clock adjusts for the 8051 clock rate 48 24 12 MHz such that it always presents the correct frequency for 230 KBaud operatio...

Page 8: ...initial download step has occurred Two control bits in the USBCS USB Control and Status register control the ReNumeration process DISCON and RENUM To simulate a USB disconnect the firmware sets DISCON...

Page 9: ...e 2 04 SOF Start of Frame or microframe 3 08 SUTOK Setup Token Received 4 0C SUSPEND USB Suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high speed operation 7 18 EP0ACK FX2 ACK d the CO...

Page 10: ...illator and PLL When WAKEUP is asserted by external logic the oscillator restarts and after the PLL stabilizes and the 8051 receives a wakeup interrupt This applies whether or not FX2 is connected to...

Page 11: ...scratch pad 0 5 kbytes RAM spaces have the following access USB download USB upload Setup data pointer I2 C compatible interface boot load Figure 3 1 Internal Code Memory EA 0 Inside FX2 Outside FX2...

Page 12: ...l Code Memory EA 1 Inside FX2 Outside FX2 7 5 kbytes USB regs and 4k EP buffers RD WR 0 5 kbytes RAM Data RD WR OK to populate data memory here RD WR strobes are not active 48 kbytes External Data Mem...

Page 13: ...e either double triple or quad buffered For high speed endpoint configuration options see Figure 3 3 3 11 3 Setup Data Buffer A separate eight byte buffer at 0xE6B8 0xE6BF holds the SETUP data from a...

Page 14: ...columns may be chosen 3 11 5 Default Full Speed Alternate Settings Notes 1 0 means not implemented 2 2x means double buffered Table 3 4 Default Full Speed Alternate Settings 1 2 Alternate Setting 0 1...

Page 15: ...m an external FIFO or other logic if desired The GPIF can be run from either an internally derived clock or externally supplied clock IFCLK at a rate that transfers data up to 96 Megabytes s 48 MHz In...

Page 16: ...GPIF decrements the value in these registers to represent the current status of the transaction 3 14 USB Uploads and Downloads The core has the ability to directly edit the data contents of the intern...

Page 17: ...of the 56 pin package in Figure 4 1 are common to all versions in the FX2 family Three modes are available in all package versions Port GPIF master and Slave FIFO These modes define the signals on th...

Page 18: ...2 D1 D0 EA 128 RD WR CS OE PSEN A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 XTALIN XTALOUT RESET WAKEUP SCL SDA IFCLK CLKOUT DPLUS DMINUS FD 15 FD 14 FD 13 FD 12 FD 11 FD 10 FD 9 FD 8 FD 7 F...

Page 19: ...T PE1 T1OUT PE2 T2OUT PE3 RXD0OUT PE4 RXD1OUT PE5 INT6 PE6 T2EX PE7 GPIFADR8 GND A4 A5 A6 A7 PD4 FD12 PD5 FD13 PD6 FD14 PD7 FD15 GND A8 A9 A10 CY7C68013 128 pin TQFP 103 104 105 106 107 108 109 110 11...

Page 20: ...D7 FD15 GND CLKOUT CY7C68013 100 pin TQFP GND VCC GND PB7 FD7 PB6 FD6 PB5 FD5 PB4 FD4 RxD1 TxD1 RxD0 TxD0 GND VCC PB3 FD3 PB2 FD2 PB1 FD1 PB0 FD0 VCC WR RD 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95...

Page 21: ...CL SDA VCC PB0 FD0 PB1 FD1 PB2 FD2 PB3 FD3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PD4 FD12 PD3 FD11 PD2 FD10 PD1 FD9 PD0 FD8 WAKEUP VCC RESET GND PA7 FLAGD...

Page 22: ...xternal 8051 program and data memory The data bus is active only for external bus accesses and is driven LOW in suspend 60 D1 I O Z Z 61 D2 I O Z Z 62 D3 I O Z Z 63 D4 I O Z Z 86 D5 I O Z Z 87 D6 I O...

Page 23: ...dge triggered IT1 1 or level triggered IT1 0 84 69 42 PA2 or SLOE I O Z I PA2 Multiplexed pin whose function is selected by two bits IFCONFIG 1 0 PA2 is a bidirectional IO port pin SLOE is an input on...

Page 24: ...55 45 30 PB5 or FD 5 I O Z I PB5 Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 PB5 is a bidirectional I O port pin FD 5 is the bidirectional FIFO GPIF data bus 56 46 31...

Page 25: ...5 or FD 13 I O Z I PD5 Multiplexed pin whose function is selected by the IFCONFIG 1 0 and EPxFIFCFG 0 wordwide bits FD 13 is the bidirectional FIFO GPIF data bus 123 97 2 PD6 or FD 14 I O Z I PD6 Mult...

Page 26: ...4 3 8 RDY0 or SLRD Input N A Multiplexed pin whose function is selected by the following bits IFCONFIG 1 0 RDY0 is a GPIF input signal SLRD is the input only read strobe with programmable polarity FIF...

Page 27: ...ides data to the UART in all modes 52 42 TXD1 Output H TXD1is an active HIGH output pin from 8051 UART1 which provides the output clock in sync mode and the output data in async mode 51 41 RXD0 Input...

Page 28: ...Power N A VCC Connect to 3 3V power source 3 2 4 GND Ground N A Ground 20 19 7 GND Ground N A Ground 27 21 17 GND Ground N A Ground 49 39 19 GND Ground N A Ground 58 48 33 GND Ground N A Ground 65 50...

Page 29: ...SIZE 0 BUF1 BUF0 10100010 bbbbbrbb E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr E614 1 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0...

Page 30: ...d Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx R W E649 7 OUTPKTEND 6 Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W INTERRUPTS E650 1 EP2FIFOIE 6 Endpoint 2 slave FIFO Flag Interrupt Enable 0 0 0...

Page 31: ...C6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW E68C 1 reserved E68D 1 EP1OUTBC Endpoint 1 OUT Byte Count 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW E68E 1 reserved E68F 1 EP1INBC Endpoint 1 IN Byte Count 0 BC6...

Page 32: ...FLOWSTATE Flowstate Enable and Selec tor FSE 0 0 0 0 FS2 FS1 FS0 00000000 brrrrbbb E6C7 1 FLOWLOGIC Flowstate Logic LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW E6C8 1 FLOWEQ0C...

Page 33: ...xxxxxxx RW FC00 512 EP8FIFOBUF 512 byte EP 8 slave FIFO buffer IN or OUT D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW FE00 512 reserved xxxx I C Compatible Configuration Byte 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx...

Page 34: ...1 PT0 PX0 10000000 RW B9 1 reserved BA 1 EP01STAT 7 Endpoint 0 1 Status 0 0 0 0 0 EP1INBSY EP1OUTBSY EP0BSY 00000000 R BB 1 GPIFTRIG 7 6 Endpoint 2 4 6 8 GPIF slave FIFO Trigger DONE 0 0 0 0 RW EP1 EP...

Page 35: ...0V to 3 6V Ground Voltage 0V FOSC Oscillator or Crystal Frequency 24 MHz 100 ppm Parallel Resonant 8 0 DC Characteristics 8 1 USB Transceiver USB 2 0 compliant in full and high speed modes Table 8 1...

Page 36: ...tAV tDSU 43 ns Table 9 1 Program Memory Read Parameters Parameter Description Min Typ Max Unit Notes tCL 1 CLKOUT Frequency 20 83 ns 48 MHz 41 66 ns 24 MHz 83 2 ns 12 MHz tAV Delay from Clock to Valid...

Page 37: ...ption Min Typ Max Unit Notes tCL 1 CLKOUT Frequency 20 83 ns 48 MHz 41 66 ns 24 MHz 83 2 ns 12 MHz tAV Delay from Clock to Valid Address 10 7 ns tSTBL Clock to RD LOW 11 ns tSTBH Clock to RD HIGH 11 n...

Page 38: ...s 0 10 7 ns tSTBL Clock to WR Pulse LOW 0 11 2 ns tSTBH Clock to WR Pulse HIGH 0 11 2 ns tSCSL Clock to CS Pulse LOW 13 0 ns tON1 Clock to Data Turn on 0 13 1 ns tOFF1 Clock to Data Hold Time 0 13 1 n...

Page 39: ...Clock to GPIF Address Propagation Delay 7 5 ns tXGD Clock to GPIF Data Output Propagation Delay 11 ns tXCTL Clock to CTLX Output Propagation Delay 6 7 ns Table 9 5 GPIF Synchronous Signals Parameters...

Page 40: ...on Delay 9 5 ns tXFD Clock to FIFO Data Output Propagation Delay 11 ns Table 9 7 Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK 14 Parameter Description Min Max Unit tIFCLK IFCLK...

Page 41: ...rn on to FIFO Data Valid 10 5 ns tOEoff SLOE Turn off to FIFO Data Hold 10 5 ns Table 9 9 Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK 14 Parameter Description Min Max Unit tI...

Page 42: ...ternally Sourced IFCLK 15 Parameter Description Min Max Unit tWRpwl SLWR Pulse LOW 50 ns tWRpwh SLWR Pulse HIGH 70 ns tSFD SLWR to FIFO DATA Set up Time 10 ns tFDH FIFO DATA to SLWR Hold Time 10 ns tX...

Page 43: ...e FIFO Asynchronous Packet End Strobe Parameters 15 Parameter Description Min Max Unit tPEpwl PKTEND Pulse Width LOW 50 ns tPWpwh PKTEND Pulse Width HIGH 50 ns tXFLG PKTEND to FLAGS Output Propagation...

Page 44: ...1 0 to Clock Set up Time 25 ns tFAH Clock to FIFOADR 1 0 Hold Time 10 ns Table 9 18 Slave FIFO Asynchronous Address Parameters 15 Parameter Description Min Max Unit tSFA FIFOADR 1 0 to RD WR PKTEND Se...

Page 45: ...8013 Document 38 08012 Rev A Page 45 of 48 11 0 Package Diagrams The FX2 is available in three packages 56 pin SSOP 100 pin TQFP 128 pin TQFP 51 85062 C Figure 11 1 56 lead Shrunk Small Outline Packag...

Page 46: ...CY7C68013 Document 38 08012 Rev A Page 46 of 48 51 85050 A Figure 11 2 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm A101...

Page 47: ...r The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor again...

Page 48: ...Controller Document Number 38 08012 REV ECN NO Issue Date Orig of Change Description of Change 111753 11 15 01 DSG Change from Spec number 38 00929 to 38 08012 A 111802 02 20 02 KKU Update functional...

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