Cypress CY7C68013, Manual

Page: 29 / 48

CY7C68013
Document #: 38-08012 Rev. *A Page 29 of 48
5.0 Register Summary
FX2 register bit definitions are described in the FX2 TRM in greater detail.
Table 5-1. FX2 Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
GPIF Waveform Memories
E400 128 WAVEDATA GPIF Waveform Descriptor
0, 1, 2, 3 data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E480 384 reserved
GENERAL CONFIGURATION
E600 1 CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr
E601 1 IFCONFIG Interface Configuration
(Ports, GPIF, slave FIFOs) IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 11000000 RW
E602 1 PINFLAGSAB
[ 6]
Slave FIFO FLAGA and
FLAGB Pin Configuration FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW
E603 1 PINFLAGSCD
[ 6]
Slave FIFO FLAGC and
FLAGD Pin Configuration FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 01000000 RW
E604 1 FIFORESET
[ 6]
Restore FIFOS to default
state NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E605 1 BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 0 00000000 rrrrbbbr
E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1 BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1 UART230 230 Kbaud internally
generated ref. clock 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
E609 1 FIFOPINPOLAR
[ 6]
Slave FIFO Interface pins
polarity 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb
E60A 1 REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 Rev A, B -
00000000
Rev C, D -
00000010
Rev E -
00000100
R
E60B 1 REVCTL
[ 6]
Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
UDMA
E60C 1 GPIFHOLDTIME MSTB Hold Time (for UDMA) 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3 reserved
ENDPOINT CONFIGURATION
E610 1 EP1OUTCFG Endpoint 1-OUT Configura-
tion VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E611 1 EP1INCFG Endpoint 1-IN Configuration VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb
E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr
E614 1 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 11100010 bbbbbrbb
E615 1 EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr
2 reserved
E618 1 EP2FIFOCFG
[ 6]
Endpoint 2 / slave FIFO con-
figuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E619 1 EP4FIFOCFG
[ 6]
Endpoint 4 / slave FIFO con-
figuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E61A 1 EP6FIFOCFG
[ 6]
Endpoint 6 / slave FIFO con-
figuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
E61B 1 EP8FIFOCFG
[ 6]
Endpoint 8 / slave FIFO con-
figuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
4 reserved
E620 1 EP2AUTOINLENH
[ 6]
Endpoint 2 AUTOIN Packet
Length H 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E621 1 EP2AUTOINLENL
[ 6]
Endpoint 2 AUTOIN Packet
Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E622 1 EP4AUTOINLENH
[ 6]
Endpoint 4 AUTOIN Packet
Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E623 1 EP4AUTOINLENL
[ 6]
Endpoint 4 AUTOIN Packet
Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E624 1 EP6AUTOINLENH
[ 6]
Endpoint 6 AUTOIN Packet
Length H 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E625 1 EP6AUTOINLENL
[ 6]
Endpoint 6 AUTOIN Packet
Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E626 1 EP8AUTOINLENH
[ 6]
Endpoint 8 AUTOIN Packet
Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E627 1 EP8AUTOINLENL
[ 6]
Endpoint 8 AUTOIN Packet
Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
8 reserved
E630
H.S.
1 EP2FIFOPFH
[ 6]
Endpoint 2 / slave FIFO Pro-
grammable Flag H DECIS PKTSTAT IN:PKTS[2]
OUT:PFC12
IN:PKTS[1]
OUT:PFC11
IN:PKTS[0]
OUT:PFC10
0 PFC9 PFC8 10001000 bbbbbrbb
E630
F.S.
1 EP2FIFOPFH
[ 6]
Endpoint 2 / slave FIFO Pro-
grammable Flag H DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 IN:PKTS[2]
OUT:PFC8
10001000 bbbbbrbb
E631
H.S.
1 EP2FIFOPFL
[ 6]
Endpoint 2 / slave FIFO Pro-
grammable Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
Note:
6. Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”