CY7C68013
Document #: 38-08012 Rev. *A
Page 26 of 48
111
89
PE3 or
RXD0OUT
I/O/Z
I
(PE3)
Multiplexed pin whose function is selected by the PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT
is selected and UART0 is in Mode 0, this pin provides the output data
for UART0 only when it is in sync mode. Otherwise it is a 1.
112
90
PE4 or
RXD1OUT
I/O/Z
I
(PE4)
Multiplexed pin whose function is selected by the PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in Mode 0, this pin provides the
output data for UART1 only when it is in sync mode. In Modes 1, 2,
and 3, this pin is HIGH.
113
91
PE5 or
INT6
I/O/Z
I
(PE5)
Multiplexed pin whose function is selected by the PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin is
edge-sensitive, active HIGH.
114
92
PE6 or
T2EX
I/O/Z
I
(PE6)
Multiplexed pin whose function is selected by the PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX reloads
timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set
in T2CON.
115
93
PE7 or
GPIFADR8
I/O/Z
I
(PE7)
Multiplexed pin whose function is selected by the PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
4
3
8
RDY0 or
SLRD
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPOLAR.3) for the slave FIFOs connected to FDI[0..7] or
FDI[0..15].
5
4
9
RDY1 or
SLWR
Input
N/A
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPOLAR.2) for the slave FIFOs connected to FDI[0..7] or
FDI[0..15].
6
5
RDY2
Input
N/A
RDY2 is a GPIF input signal.
7
6
RDY3
Input
N/A
RDY3 is a GPIF input signal.
8
7
RDY4
Input
N/A
RDY4 is a GPIF input signal.
9
8
RDY5
Input
N/A
RDY5 is a GPIF input signal.
69
54
36
CTL0 or
FLAGA
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0]
pins.
70
55
37
CTL1 or
FLAGB
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
71
56
38
CTL2 or
FLAGC
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
Table 4-1. FX2 Pin Descriptions
[5]
(continued)
128
100
56
Name
Type
Default
Description
