Cypress CY7C68013, Manual

Page: 17 / 48

CY7C68013
Document #: 38-08012 Rev. *A Page 17 of 48
3.16.2 I
2
C-compatible Interface Boot Load Access
At power-on reset the I
2
C-compatible interface boot loader will load the VID/PID/DID/a configuration byte and up to 8 kbytes of
program/data. The available RAM spaces are 8 kbytes from 0x0000–0x1FFF and 512 bytes from 0xE000–0xE1FF. The 8051 will
be in reset. I
2
C-compatible interface boot loads only occur after power-on reset.
3.16.3 I
2
C-compatible Interface General Purpose Access
The 8051 can control peripherals connected to the I
2
C-compatible bus using the I2CTL and I2DAT registers. FX2 provides I
2
C
compatible master control only, it is never an I
2
C-compatible slave.
4.0 Pin Assignments
Figure 4-1 identifies all signals for the three package types. The following pages illustrate the individual pin diagrams, plus a
combination diagram showing which of the full set of signals are available in the 128-, 100-, and 56-pin packages.
The 56-pin package is the lowest-cost version. The signals on the left edge of the 56-pin package in Figure 4-1 are common to
all versions in the FX2 family. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These
modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register
bits. Port mode is the power-on default configuration.
The 100-pin package adds functionality to the 56-pin package by adding these pins:
• PORTC or alternate GPIFADR[7...0] address signals
• PORTE or alternate GPIFADR8 address signals and 7 more 8051 signals
• 3 GPIF Control signals
• 4 GPIF Ready signals
• Nine 8051 signals (two USARTs, three timer inputs, INT4,and INT5#)
• BKPT, RD#, WR#
The 128-pin package is the full version, adding the 8051 address and data buses plus control signals. Note that two of the required
signals, RD# and WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to
pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC.
Note:
4. This EEPROM does not have address pins.
Table 3-6. Strap Boot EEPROM Address Lines to These Values
Bytes Example EEPROM A2 A1 A0
16 24LC00
[4]
N/A N/A N/A
128 24LC01 0 0 0
256 24LC02 0 0 0
4K 24LC32 0 0 1
8K 24LC64 0 0 1