Cypress CY14E256L Specification Sheet Download | Manualshive

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CY14E256L

Document Number: 001-06968 Rev. *F

Page 16 of 18

Figure 15. 32-Pin (300 Mil) CDIP (001-51694)

Package Diagram

(continued)

001-51694 **

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Summary of Contents for CY14E256L

Page 1: ...fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation tak...

Page 2: ... the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state VSS Ground Ground for the Device The device is connected to ground of the system VCC Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output i...

Page 3: ...3 AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E256L During normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically disc...

Page 4: ... software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled until the cycle is completed Because a sequence of READs from specif...

Page 5: ...are only initiated by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the CY14E256L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 4 shows the relationship between ICC and READ or WRITE cycle time Worst case current consumption is shown for both CMOS and TTL input levels comm...

Page 6: ...s to meet this requirementandnotexceedthe maximumVCAP valuebecause the higher inrush currents may reduce the reliability of the internal pass transistor Customers that want to use a larger VCAP value to make sure there is extra store charge should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period Table 1 Hardware Mode S...

Page 7: ...rcial 97 80 70 mA mA Industrial 100 85 70 mA mA mA ICC2 Average VCC Current during STORE All Inputs Do Not Care VCC Max Average current for duration tSTORE 3 mA ICC3 Average VCC Current at tRC 200 ns 5V 25 C Typical WE VCC 0 2V All other inputs cycling Dependent on output loading and cycle rate Values obtained without output loads 10 mA ICC4 Average VCAP Current during AutoStore Cycle All Inputs D...

Page 8: ...following table the thermal resistance parameters are listed 8 Parameter Description Test Conditions 32 SOIC 32 CDIP Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 35 45 TBD C W ΘJC Thermal Resistance Junction to Case 13 26 TBD C W Figure 6 AC Test Loads AC Test Conditions DC Electrical Char...

Page 9: ...Active 5 5 5 ns tHZCE 11 tEHQZ Chip Disable to Output Inactive 10 13 15 ns tLZOE 11 tGLQX Output Enable to Output Active 0 0 0 ns tHZOE 11 tGHQZ Output Disable to Output Inactive 10 13 15 ns tPU 8 tELICCH Chip Enable to Power Active 0 0 0 ns tPD 8 tEHICCL Chip Disable to Power Standby 25 35 45 ns Switching Waveforms Figure 7 SRAM Read Cycle 1 Address Controlled 9 10 Figure 8 SRAM Read Cycle 2 CE a...

Page 10: ...Write 0 0 0 ns tHA tWHAX tEHAX Address Hold After End of Write 0 0 0 ns tHZWE 11 12 tWLQZ Write Enable to Output Disable 10 13 15 ns tLZWE 11 tWHQX Output Active After End of Write 5 5 5 ns Switching Waveforms Figure 9 SRAM Write Cycle 1 WE Controlled 13 14 Figure 10 SRAM Write Cycle 2 CE Controlled 13 14 tWC tSCE tHA tAW tSA tPWE tSD tHD tHZWE tLZWE ADDRESS CE WE DATA IN DATA OUT DATA VALID HIGH ...

Page 11: ...Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 6 V tVCCRISE VCC Rise Time 150 μs tVSBL 13 Low Voltage Trigger VSWITCH to HSB low 300 ns Switching Waveforms Figure 11 AutoStore Power Up RECALL WE Notes 15 tHRECALL starts from the time VCC rises above VSWITCH 16 CE and OE low and WE high for output behavior 17 HSB is asserted low for 1us when VCAP drops through VSWITCH If an SRAM W...

Page 12: ... ns tHACE 18 19 tELAX Address Hold Time 20 20 20 ns tRECALL RECALL Duration 20 20 20 μs Switching Waveforms Figure 12 CE Controlled Software STORE RECALL Cycle 19 tRC tRC tSA tSCE tHACE tSTORE tRECALL DATA VALID DATA VALID 6 S S E R D D A 1 S S E R D D A HIGH IMPEDANCE ADDRESS CE OE DQ DATA Notes 18 The software sequence is clocked on the falling edge of CE without involving OE double clocking abo...

Page 13: ...n CY14E256L Unit Min Max tDHSB 16 20 tRECOVER tHHQX Hardware STORE High to Inhibit Off 700 ns tPHSB tHLHX Hardware STORE Pulse Width 15 ns tHLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveforms Figure 13 Hardware STORE Cycle Note 20 tDHSB is only applicable after tSTORE is complete Feedback ...

Page 14: ...l 45 CY14E256L SZ45XCT 51 85127 32 pin SOIC 300 mil Commercial CY14E256L SZ45XC 51 85127 32 pin SOIC 300 mil CY14E256L SZ45XIT 51 85127 32 pin SOIC 300 mil Industrial CY14E256L SZ45XI 51 85127 32 pin SOIC 300 mil CY14E256L D45XI 001 51694 32 pin CDIP 300 mil All parts are Pb free The above table contains Final information Please contact your local Cypress sales representative for availability of t...

Page 15: ...SIONS IN INCHES MM MIN MAX 0 292 7 416 0 299 7 594 0 405 10 287 0 419 10 642 0 050 1 270 TYP 0 090 2 286 0 100 2 540 0 004 0 101 0 0100 0 254 0 006 0 152 0 012 0 304 0 021 0 533 0 041 1 041 0 026 0 660 0 032 0 812 0 004 0 101 REFERENCE JEDEC MO 119 PART S32 3 STANDARD PKG SZ32 3 LEAD FREE PKG 0 014 0 355 0 020 0 508 0 810 20 574 0 822 20 878 51 85127 A Feedback ...

Page 16: ...CY14E256L Document Number 001 06968 Rev F Page 16 of 18 Figure 15 32 Pin 300 Mil CDIP 001 51694 Package Diagram continued 001 51694 Feedback ...

Page 17: ...taining to OE controlled Software STORE and RECALL operation Changed the address locations of the software STORE RECALL com mand Updated Part Nomenclature Table and Ordering Information Table D 1349963 See ECN UHA SFV Changed from Preliminary to Final Updated AC Test Conditions Updated Ordering Information Table E 2427986 See ECN GVCH Move to external web F 2606744 02 19 09 GVCH PYRS Updated Featu...

Page 18: ...or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED W...

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