Cypress AutoStore STK17TA8 Specification Sheet Download

Page: 19 / 23

STK17TA8

Document #: 001-52039 Rev. **

Page 19 of 23

0x1FFF7

Watchdog Timer

WDS

WDW

WDT

WDS

Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automatically

once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.

WDW

Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0). This

allows the user to strobe the watchdog stobe bit without disturbing the time-out value. Set this bit to 0 to allow bits

5-0 to be written.

WDT

Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents

a multiplier of the 32 Hz count (31.25 ms). The range of time-out values is 31.25 ms (a setting of 1) to 2 seconds

(setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the

WDW bit was cleared to 0 on a previous cycle.

0x1FFF6

Interrupt

WIE

AIE

PFIE

ABE

H/L

P/L

WIE

Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin

as well as setting the WDF flag. When set to 0, the watchdog time-out only sets the WDF flag.

AIE

Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as setting the AF flag. When set

to 0, the alarm match only affects the AF flag.

PFIE

Power-Fail Enable. When set to 1, a power failure drives the INT pin as well as setting the PF flag. When set to 0,

the power failure only sets the PF flag.

Reserved For Future Used

H/L

High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active low.

P/L

Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approxi-

mately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags register is read.

0x1FFF5

Alarm – Day

10s Alarm Date

Alarm Date

Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.

Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the

match circuit to ignore the date value.

0x1FFF4

Alarm – Hours

10s Alarm Hours

Alarm Hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the

match circuit to ignore the hours value.

0x1FFF4

Alarm – Hours

10s Alarm Hours

Alarm Hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the

match circuit to ignore the hours value.

Register Map Detail

(continued)

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Summary of Contents for AutoStore STK17TA8

Page 1: ...s a fast static RAM with a nonvolatile Quantum Trap storage element included with each memory cell The SRAM provides the fast access and cycle times ease of use and unlimited read and write endurance of a normal SRAM Data transfers automatically to the nonvolatile storage cells when power loss is detected the STORE operation On power up data is automatically restored to the SRAM the RECALL operati...

Page 2: ... asserting G high caused the DQ pins to tri state X1 Output Crystal Connection drives crystal on startup X2 Input Crystal Connection for 32 768 kHz crystal VRTCcap Power Supply Capacitor supplied backup RTC supply voltage Left unconnected if VRTCbat is used VRTCbat Power Supply Battery supplied backup RTC supply voltage Left unconnected if VRTCcap is used VCC Power Supply Power 3 0V 20 10 HSB I O ...

Page 3: ...t loading and cycle rate Values obtained without output loads ICC2 Average VCC Current during STORE 3 3 mA All Inputs Don t Care VCC max Average current for duration of STORE cycle tSTORE ICC3 Average VCC Current at tAVAV 200ns 3V 25 C Typical 10 10 mA W V CC 0 2V All Other Inputs Cycling at CMOS Levels Dependent on output loading and cycle rate Values obtained without output loads ICC4 Average VC...

Page 4: ... 6 2 7 3 6 V 3 0V 20 10 VCAP Storage Capacitance 17 57 17 57 μF Between VCAP pin and VSS 5V rated NVC Nonvolatile STORE operations 200 200 K DATAR Data Retention 20 20 Years At 55 C DC Electrical Characteristics continued VCC 2 7V 3 6V Symbol Parameter Commercial Industrial Units Notes Min Max Min Max Notes 2 These parameters are guaranteed but not tested Symbol Parameter Max Units Conditions CIN ...

Page 5: ... Battery Pin Voltage 1 8 3 3 1 8 3 3 V Typical 3 0 Volts during normal operation VRTCcap RTC Capacitor Pin Voltage 1 2 2 7 1 2 2 7 V Typical 2 4 Volts during normal operation tOSCS RTC Oscillator time to start 10 10 sec At MIN Temperature from Power up or Enable 5 5 sec At 25 C from Power up or Enable C 1 C 2 RF Y 1 X1 X2 Recommended Values Y1 32 768 KHz 10M Ohm 0 install cap footprint but leave u...

Page 6: ...e Access Time 25 45 ns 2 tAVAV 3 tELEH 3 tRC Read Cycle Time 25 45 ns 3 tAVQV 4 tAVQV 4 tAA Address Access Time 25 45 ns 4 tGLQV tOE Output Enable to Data Valid 12 20 ns 5 tAXQX 4 tAXQX 4 tOH Output Hold after Address Change 3 3 ns 6 tELQX tLZ Address Change or Chip Enable to Output Active 3 3 ns 7 tEHQZ 5 tHZ Address Change or Chip Disable to Output Inactive 10 15 ns 8 tGLQX tOLZ Output Enable to...

Page 7: ...0 30 ns 15 tDVWH tDVEH tDW Data Set up to End of Write 10 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 ns 17 tAVWH tAVEH tAW Address Set up to End of Write 20 30 ns 18 tAVWL tAVEL tAS Address Set up to Start of Write 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 ns 20 tWLQZ 5 7 tWZ Write Enable to Output Disable 10 15 ns 21 tWHQX tOW Output Active after End of Write 3 ...

Page 8: ... cycle no STORE will take place 11 Industrial Grade Devices require 15 ms MAX NO Symbols Parameter STK17TA8 Units Notes Standard Alternate Min Max 22 tHRECALL Power up RECALL Duration 40 ms 9 23 tSTORE tHLHZ STORE Cycle Duration 12 5 ms 10 11 24 VSWITCH Low Voltage Trigger Level 2 65 V 25 VCCRISE VCC Rise Time 150 μS NOTE Read and Write cycles will be ignored during STORE RECALL and while VCC is b...

Page 9: ...Max Min Max 26 tAVAV tAVAV tRC STORE RECALL Initiation Cycle Time 25 45 ns 13 27 tAVEL tAVGL tAS Address Set up Time 0 0 ns 28 tELEH tGLGH tCW Clock Pulse Width 20 30 ns 29 tEHAX tGHAX Address Hold Time 1 1 ns 30 tRECALL tRECALL RECALL Duration 100 100 μs 26 26 27 28 29 23 30 26 26 27 28 29 23 30 Notes 12 The software sequence is clocked on the falling edge of E controlled READs or G controlled RE...

Page 10: ...1 Notes 14 On a hardware STORE initiation SRAM operation continues to be enabled for time tDELAY to allow READ WRITE cycles to compete 15 This is the amount of time that it takes to take action on a soft sequence command Vcc power must remain high to effectively register command 16 Commands like Store and Recall lock out I O until operation is complete which further increases this time See specifi...

Page 11: ...0x08FC0 Nonvolatile Store Output High Z ICC2 L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x04C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall Output Data Output Data Output Data Output Data Output Data Output High Z Active 17 18 19 Notes 17 The six consecutive addresses must be in the order listed W must be high during all six consecutive cycles to enable a nonvolatile cy...

Page 12: ...p to perform a single STORE operation If the voltage on the VCC pin drops below VSWITCH the part automatically disconnects the VCAP pin from VCC A STORE operation is initiated with power provided by the VCAP capacitor Figure 14 shows the proper connection of the storage capacitor VCAP for automatic store operation Refer to the DC Electrical Characteristics on page 3 for the size of the capacitor T...

Page 13: ...he AutoStore function cannot be disabled on the STK17TA8 Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and ...

Page 14: ... capacitor power source connect the capacitor to the VRTCcap pin and leave the VRTCbat pin unconnected Capacitor backup time values based on maximum current specs are shown below Nominal times are approximately three times longer A capacitor has the obvious advantage of being more reliable and not containing hazardous materials The capacitor is recharged every time the power is turned on so that r...

Page 15: ...ent real time clock register Using the match bits the alarm can occur as specifically as one particular second on one day of the month or as frequently as once per minute Note The product requires the match bit for seconds 1x1FFF2 D7 be set to 0 for proper operation of the Alarm Flag and Interrupt The alarm value should be initialized on power up by software since the alarm registers are not nonvo...

Page 16: ...wer monitor circuit When set to 0 only the PF flag is set High Low H L When set to a 1 the INT pin is active high and the driver mode is push pull The INT pin can drive high only when VCC VSWITCH When set to a 0 the INT pin is active low and the drive mode is open drain The active low open drain output is maintained even when power is lost Pulse Level P L When set to a 1 the INT pin is driven for ...

Page 17: ...s 00 99 0x1FFFE 0 0 0 10s Months Months Months 01 12 0x1FFFD 0 0 10s Day of Month Day of Month Day of Month 01 31 0x1FFFC 0 0 0 0 0 Day of Week Day of week 01 07 0x1FFFB 0 0 10s Hours Hours Hours 00 23 0x1FFFA 0 10s Minutes Minutes Minutes 00 59 0x1FFF9 0 10s Seconds Seconds Seconds 00 59 0x1FFF8 OSCEN 0 0 Cal Sign Calibration 00000 Calibration values 0x1FFF7 WDS WDW WDT Watchdog 0x1FFF6 WIE 0 AIE...

Page 18: ...r must assign meaning to the day value as the day is not integrated with the date 0x1FFFB Real Time Clock Hours D7 D6 D5 D4 D3 D2 D1 D0 0 0 10s Hours Hours Contains the BCD value of hours in 24 hour format Lower nibble contains the lower digit and operates from 0 to 9 upper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 0x1FFFA Real Time Clock ...

Page 19: ...fects the AF flag PFIE Power Fail Enable When set to 1 a power failure drives the INT pin as well as setting the PF flag When set to 0 the power failure only sets the PF flag 0 Reserved For Future Used H L High Low When set to a 1 the INT pin is driven active high When set to 0 the INT pin is open drain active low P L Pulse Level When set to a 1 the INT pin is driven active determined by H L by an...

Page 20: ...register is read or on power up PF Power fail Flag This read only bit is set to 1 when power falls below the power fail threshold VSWITCH It is cleared to 0 when the Flags register is read or on power up OSCF Oscillator Fail Flag Set to 1 on power up only if the oscillator is enabled and not running in the first 5ms of operation This indicates that RTC backup power failed and clock value is no lon...

Page 21: ...erature STK17TA8 RF25 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Commercial STK17TA8 RF45 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Commercial STK17TA8 RF25TR 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Commercial STK17TA8 RF45TR 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 45 Commercial STK17TA8 RF25I 3V 128Kx8 AutoStore nvSRAM RTC SSOP48 300 25 Industrial STK17TA8 RF45I 3V 128Kx8 AutoStore nv...

Page 22: ...STK17TA8 Document 001 52039 Rev Page 22 of 23 Package Diagrams Figure 17 48 Pin SSOP 51 85061 51 85061 C Feedback ...

Page 23: ...the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU...

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