STK17TA8
Document #: 001-52039 Rev. **
Page 6 of 23
SRAM READ Cycles #1 and #2
Figure 5. SRAM READ Cycle #1:
Address Controlled
[3, 4, 6]
Figure 6. SRAM READ Cycle #2:
E and G
Controlled
[3, 6]
Notes
3. W must be high during SRAM READ cycles.
4. Device is continuously selected with E and G both low
5. Measured
±
200mV from steady state output voltage.
6. HSB must remain high during READ and WRITE cycles.
NO.
Symbols
Parameter
STK17TA8-25 STK17TA8-45
Units
#1
#2
Alt.
Min
Max
Min
Max
1
t
ELQV
t
ACS
Chip Enable Access Time
25
45
ns
2
t
AVAV
[3]
t
ELEH
[3]
t
RC
Read Cycle Time
25
45
ns
3
t
AVQV
[4]
t
AVQV
[4]
t
AA
Address Access Time
25
45
ns
4
t
GLQV
t
OE
Output Enable to Data Valid
12
20
ns
5
t
AXQX
[4]
t
AXQX
[4]
t
OH
Output Hold after Address Change
3
3
ns
6
t
ELQX
t
LZ
Address Change or Chip Enable to Output Active
3
3
ns
7
t
EHQZ
[5]
t
HZ
Address Change or Chip Disable to Output
Inactive
10
15
ns
8
t
GLQX
t
OLZ
Output Enable to Output Active
0
0
ns
9
t
GHQZ
[5]
t
OHZ
Output Disable to Output Inactive
10
15
ns
10
t
ELICCL
[2]
t
PA
Chip Enable to Power Active
0
0
ns
11
t
EHICCH
[2]
t
PS
Chip Disable to Power Standby
25
45
ns
DATA VALID
5
t
AXQX
3
t
AVQV
DQ (DATA OUT)
ADDRESS
2
t
AVAV
2
29
11
7
9
10
8
4
3
6
1
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