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CY7C1231H

Document #: 001-00207 Rev. *B

Page 9 of 12

Switching Waveforms

Read/Write Waveforms

[18, 19, 20]

Notes: 

18. For this waveform ZZ is tied LOW.
19. When CE is LOW, CE

1

 is LOW, CE

2

 is HIGH and CE

3

 is LOW. When CE is HIGH, CE

1

 is HIGH or CE

is LOW or CE

3

 is HIGH.

20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

WRITE

D(A1)

1

2

3

4

5

6

7

8

9

CLK

tCYC

tCL

tCH

10

CE

tCEH

tCES

WE

CEN

tCENH

tCENS

BW

[A:B]

ADV/LD

tAH

tAS

ADDRESS

A1

A2

A3

A4

A5

A6

A7

tDH

tDS

DQ

COMMAND

tCLZ

D(A1)

D(A2)

Q(A4)

Q(A3)

D(A2+1)

tDOH

tCHZ

tCDV

WRITE

D(A2)

BURST
WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE

tOEV

tOELZ

tOEHZ

DON’T CARE

UNDEFINED

D(A5)

tDOH

Q(A4+1)

D(A7)

Q(A6)

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Summary of Contents for CY7C1231H

Page 1: ...g transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs...

Page 2: ...NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE NC 18...

Page 3: ...uring the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When ass...

Page 4: ...HIGH input on ADV LD will increment the internal burst counter regardless of the state of Chip Enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or...

Page 5: ...READ Continue Burst Next X X X L H X X H L L H Tri State WRITE Cycle Begin Burst External L H L L L L L X L L H Data In D WRITE Cycle Continue Burst Next X X X L H X L X L L H Data In D NOP WRITE ABO...

Page 6: ...H Voltage for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V VIL Input LOW Voltage 9 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input...

Page 7: ...ow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 11 Tested initially an...

Page 8: ...after CLK Rise 0 5 ns tWEH WE BW A B Hold after CLK Rise 0 5 ns tCENH CEN Hold after CLK Rise 0 5 ns tDH Data Input Hold after CLK Rise 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 ns Notes 12 Tim...

Page 9: ...nce is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A B ADV LD tAH tAS...

Page 10: ...uth Table for all possible signal conditions to deselect the device 23 I Os are in tri state when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK C...

Page 11: ...ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Ordering Information Not all of the spee...

Page 12: ...conductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 100 MHz Speed bin Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and...

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