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CY7C1231H

Document #: 001-00207 Rev. *B

Page 2 of 12

Selection Guide

133 MHz

Unit

Maximum Access Time

6.5

ns

Maximum Operating Current 

225

mA

Maximum CMOS Standby Current

40

mA

Pin Configuration 

100-pin TQFP Pinout

A

A

A

A

A1

A0

NC/

28

8M

NC/144M

V

SS

V

DD

NC(36M)

A

A

A

A

A

NC

/4

M

A

NC

NC

V

DDQ

V

SS

NC

DQP

A

DQ

A

DQ

A

V

SS

V

DDQ

DQ

A

DQ

A

V

SS

NC 

V

DD

DQ

A

DQ

A

V

DDQ

V

SS

DQ

A

DQ

A

NC

NC

V

SS

V

DDQ

NC

NC

NC

NC

NC

NC

V

DDQ

V

SS

NC

NC

DQ

B

DQ

B

V

SS

V

DDQ

DQ

B

DQ

B

NC

V

DD

NC

V

SS

DQ

B

DQ

B

V

DDQ

V

SS

DQ

B

DQ

B

DQP

B

NC

V

SS

V

DDQ

NC

NC

NC

A

A

CE

1

CE

2

NC

NC

BW

B

BW

A

CE

3

V

DD

V

SS

CLK

WE

CEN

OE

NC(18M)

A

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

10

0

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

A

NC(9M)

ADV/

LD

ZZ

MODE

NC

(72M)

CY7C1231H

 

BYTE A

BYTE B

[+] Feedback 

Summary of Contents for CY7C1231H

Page 1: ...g transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs...

Page 2: ...NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE NC 18...

Page 3: ...uring the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Synchronous Clock Enable Input active LOW When ass...

Page 4: ...HIGH input on ADV LD will increment the internal burst counter regardless of the state of Chip Enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or...

Page 5: ...READ Continue Burst Next X X X L H X X H L L H Tri State WRITE Cycle Begin Burst External L H L L L L L X L L H Data In D WRITE Cycle Continue Burst Next X X X L H X L X L L H Data In D NOP WRITE ABO...

Page 6: ...H Voltage for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V VIL Input LOW Voltage 9 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input...

Page 7: ...ow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 11 Tested initially an...

Page 8: ...after CLK Rise 0 5 ns tWEH WE BW A B Hold after CLK Rise 0 5 ns tCENH CEN Hold after CLK Rise 0 5 ns tDH Data Input Hold after CLK Rise 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 ns Notes 12 Tim...

Page 9: ...nce is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A B ADV LD tAH tAS...

Page 10: ...uth Table for all possible signal conditions to deselect the device 23 I Os are in tri state when exiting ZZ sleep mode Switching Waveforms continued READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK C...

Page 11: ...ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders Ordering Information Not all of the spee...

Page 12: ...conductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 100 MHz Speed bin Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and...

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