CY7C1231H
Document #: 001-00207 Rev. *B
Page 10 of 12
NOP, STALL and Deselect Cycles
[18, 19, 21]
ZZ Mode Timing
[22, 23]
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.
23. I/Os are in tri-state when exiting ZZ sleep mode.
Switching Waveforms
(continued)
READ
Q(A3)
4
5
6
7
8
9
10
A3
A4
A5
D(A4)
1
2
3
CLK
CE
WE
CEN
BW
[A:B]
ADV/LD
ADDRESS
DQ
COMMAND
WRITE
D(A4)
STALL
WRITE
D(A1)
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tCHZ
A1
A2
Q(A2)
D(A1)
Q(A3)
tDOH
Q(A5)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
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