CyberResearch
®
Motherboards
MMGA
Series
CyberResearch, Inc
.
33
25 Business Park Drive
P: (203) 643-5000; F: (203) 643-5001
Branford, CT USA
www.cyberresearch.com
The FDD controller is interfaced to a FDD connected to the FDD connector on the MMGA.
2.8.3.5 Super I/O Fan Speed Controller
The Super I/O fan speed controller enables the system to monitor the speed of the fan.
One of the pins on the fan connector is reserved for fan speed detection and interfaced to
the fan speed controller on the Super I/O. The fan speed is then reported in the BIOS.
2.8.3.6 Super I/O Keyboard/Mouse Controller
The Super I/O keyboard/mouse controller can execute the 8042 instruction set. Some of
the keyboard controller features are listed below:
The 8042 instruction is compatible with a PS/2 keyboard and PS/2 mouse
Gate A20 and Keyboard reset output
Supports multiple keyboard power on events
Supports mouse double-click and/or mouse move power on events.
2.8.3.7 Super I/O GPIO Ports
The Super I/O has 48 programmable GPIO ports of which 8 are implemented on the
MMGA. The GPIO connector has 8 programmable bits, 4-bit input and 4-bit output.
2.8.3.8 Super I/O Infrared
The Super I/O has dedicated infrared (IrDA) pins that are interfaced to an IrDA connector.
The IrDA connector is compatible with the following standards:
ASKIR
SIR
2.8.3.9 Super I/O Parallel Port
The Super I/O parallel port (LPT) is compatible with the following LPT specifications.
SPP compatible bi-directional parallel port
Enhanced Parallel Port (EPP) mode supported. Compatible with IEEE 1284
