7. BIOS Setup
SPI-8550-LLVAS
67
POST Codes
Table 7.1.
POST Codes < 1 / 4 >
POST
(hex)
Description
02h Verify
Real
Mode
03h
Disable Non-Maskable Interrupt (NMI)
04h Get
CPU
type
06h
Initialize system hardware
07h
Disable shadow and execute code from the ROM.
08h
Initialize chipset with initial POST values
09h
Set IN POST flag
0Ah
Initialize CPU registers
0Bh
Enable CPU cache
0Ch
Initialize caches to initial POST values
0Eh Initialize
I/O
component
0Fh
Initialize the local bus IDE
10h Initialize
Power
Management
11h Load
alternate
registers
with initial POST values
12h
Restore CPU control word during warm boot
13h
Initialize PCI Bus Mastering devices
14h Initialize
keyboard
controller
16h BIOS
ROM
checksum
17h Initialize
cache
before memory Auto size
18h
8254 timer initialization
1Ah
8237 DMA controller initialization
1Ch
Reset Programmable Interrupt Controller
20h est
DRAM
refresh
22h
Test 8742 Keyboard Controller
24h
Set ES segment register to 4 GB
28h Auto
size
DRAM
29h Initialize
POST
Memory
Manager
2Ah
Clear 512 kB base RAM
2Ch
RAM failure on address line xxxx*
2Eh
RAM failure on data bits xxxx* of low byte of memory bus
2Fh
Enable cache before system BIOS shadow
32h
Test CPU bus-clock frequency
33h
Initialize Phoenix Dispatch Manager
36h
Warm start shut down
38h
Shadow system BIOS ROM
3Ah
Auto size cache
3Ch
Advanced configuration of chipset registers
3Dh
Load alternate registers with CMOS values
41h
Initialize extended memory for RomPilot
42h
Initialize interrupt vectors
45h POST
device
initialization
46h
Check ROM copyright notice
47h Initialize
I20
support
48h
Check video configuration against CMOS
Summary of Contents for SPI-8550-LLVAS
Page 7: ...vi SPI 8550 LLVAS...
Page 13: ...1 Introduction 6 SPI 8550 LLVAS...
Page 19: ...2 System Reference 12 SPI 8550 LLVAS...
Page 47: ...4 Jumper Setting 40 SPI 8550 LLVAS...