CHAPTER 6 - BIOS SETUP
PC-686 (CPCI)-LV User’s Manual
77
SDRAM CAS Latency Time
You can select CAS latency time in HCLK of 2/2 or 3/3. The system board designer
should set the values in this field, depends on the DRAM installed specifications of the
installed DRAM or the installed CPU.
The Choice: 2, 3
DRAM Data Integrity Mode
Select Parity or ECC (error-correcting code), according to the type of installed DRAM.
The Choice: Non-ECC, ECC.
System BIOS Cacheable
Selecting
Enabled
allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
The choice: Enabled, Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system
performance. However, if any program writes to this memory area, a system error
may result.
The Choice: Enabled, Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system
performance. However, if any program writes to this memory area, a system error
may result.
Summary of Contents for PC-686CPCI-LV
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Page 8: ...Table of Contents iv PC 686 CPCI LV User s Manual ...
Page 18: ...CHAPTER 1 Introduction 10 PC 686 CPCI LV User s Manual 1 7 Connector Jumper Location ...
Page 20: ...CHAPTER 1 Introduction 12 PC 686 CPCI LV User s Manual ...
Page 50: ...CHAPTER 3 Jumper Setting 42 PC 686 CPCI LV User s Manual ...
Page 72: ...CHAPTER 5 Software Utilities 64 PC 686 CPCI LV User s Manual ...
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