Copyright
©
2014
congatec
AG
TA30m16
50/95
Signal
Pin # Description
I/O
PU/PD Comment
DP
DP2_LANE1-
D42
D43
Uni-directional main link for the transport of isochronous streams and secondary data
Multiplexed with DDI and DDI2_PAIR1-
O PCIE
DP
DP2_LANE0-
D39
D40
Uni-directional main link for the transport of isochronous streams and secondary data
Multiplexed with DDI and DDI1_PAIR0-
O PCIE
DP2_HPD
D44
Detection of Hot Plug / Unplug and notification of the link layer.
Multiplexed with DDI2_HPD
I 3.3V
PD 1M
C32
Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access
I/O PCIE
PD 100k
DP2_AUX-
C33
Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access
I/O PCIE
PU 100k
3.3V
Boot strap signal (see note below).
Enable strap is already populated
DP
DP3_LANE3-
C49
C50
Uni-directional main link for the transport of isochronous streams and secondary data
Multiplexed with DDI and DDI3_PAIR3-
O PCIE
Not supported
DP
DP3_LANE2-
C46
C47
Uni-directional main link for the transport of isochronous streams and secondary data
Multiplexed with DDI and DDI3_PAIR2-
O PCIE
Not supported
DP
DP3_LANE1-
C42
C43
Uni-directional main link for the transport of isochronous streams and secondary data
Multiplexed with DDI and DDI3_PAIR1-
O PCIE
Not supported
DP
DP3_LANE0-
C39
C40
Uni-directional main link for the transport of isochronous streams and secondary data
Multiplexed with DDI and DDI3_PAIR0-
O PCIE
Not supported
DP3_HPD
C44
Detection of Hot Plug / Unplug and notification of the link layer
Multiplexed with DDI3_HPD
I 3.3V
Not supported
C36
Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access
I/O PCIE
Not supported
DP3_AUX-
C37
Half-duplex bi-directional AUX channel for services such as link configuration or
maintenance and EDID access
I/O PCIE
Not supported
Note
1. Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For
more information refer to section 8.2 "Boot Strap Signals".
2. The second DP interface is only available if LVDS is not enabled.
