Congatec 047300 User Manual Download Page 48

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TA30m16

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Table 17 HDMI Signal Descriptions

Signal

Pin # Description

I/O

PU/PD Comment

TMD

TMDS1_CLK -

D36

D37

TMDS Clock output differential pair

Multiplexed with DDI and DDI1_PAIR3-

O PCIE

TMDS

TMDS1_DATA0-

D32

D33

TMDS differential pair

Multiplexed with DDI and DDI1_PAIR2-

O PCIE

TMDS

TMDS1_DATA1-

D29

D30

TMDS differential pair

Multiplexed with DDI and DDI1_PAIR1-

O PCIE

TMDS

TMDS1_DATA2-

D26

D27

TMDS differential pair

Multiplexed with DDI and DDI1_PAIR0-

O PCIE

HDMI1_HPD

C24

TMDS Hot-plug detect

Multiplexed with DDI1_HPD

I PCIE

PD 1M

HDMI1_CTRLCLK

D15

TMDS I

C Control Clock

Multiplexed with DDI1_CTRL

I/O OD

3.3V

PU 3.0k

3.3V

HDMI1_CTRLDATA

D16

TMDS I

C Control Data

Multiplexed with DDI1_CTRLDATA_AUX-

I/O OD

3.3V

PU 3.0k

3.3V

Boot strap signal (see note below).

Enable strap is already populated

TMD

TMDS2_CLK -

D49

D50

TMDS Clock output differential pair

Multiplexed with DDI and DDI2_PAIR3-

O PCIE

TMDS

TMDS2_DATA0-

D46

D47

TMDS differential pair

Multiplexed with DDI and DDI2_PAIR2-

O PCIE

TMDS

TMDS2_DATA1-

D42

D43

TMDS differential pair

Multiplexed with DDI and DDI2_PAIR1-

O PCIE

TMDS

TMDS2_DATA2-

D39

D40

TMDS differential pair

Multiplexed with DDI and DDI2_PAIR0-

O PCIE

HDMI2_HPD

D44

TMDS Hot-plug detect

Multiplexed with DDI2_HPD

I PCIE

PD 1M

HDMI2_CTRLCLK

C32

TMDS I

C Control Clock

Multiplexed with DDI2_CTRL

I/O OD

3.3V

PU 3.0k

3.3V

HDM12_CTRLDATA

C33

TMDS I

C Control Data

Multiplexed with DDI2_CTRLDATA_AUX-

I/O OD

3.3V

PU 3.0k

3.3V

Boot strap signal (see note below).

Enable strap is already populated

TMD

TMDS3_CLK -

C49

C50

TMDS Clock output differential pair

Multiplexed with DDI and DDI3_PAIR3-

O PCIE

Not supported

TMDS

TMDS3_DATA0-

C46

C47

TMDS differential pair

Multiplexed with DDI and DDI3_PAIR2-

O PCIE

Not supported

TMDS

TMDS3_DATA1-

C42

C43

TMDS differential pair

Multiplexed with DDI and DDI3_PAIR1-

O PCIE

Not supported

TMDS

TMDS3_DATA2-

C39

C40

TMDS differential pair

Multiplexed with DDI and DDI3_PAIR0-

O PCIE

Not supported

Summary of Contents for 047300

Page 2: ...ment because the BIOS does not support this feature Added sections 9 System Resources 10 BIOS Setup Description and 11 Additional BIOS Features Official release 1 1 2015 04 15 AEM Updated the note in...

Page 3: ...ted section 7 1 Intel SoC Features Restructured the whole document Corrected typographical error in section 11 Additional BIOS Features Removed the capacity of optional eMMC from the manual 1 6 2021 0...

Page 4: ...any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing congatec AG as...

Page 5: ...hin its original packaging Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty Symbols The following symbols are used in this user s guide Warning Warnings...

Page 6: ...at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec AG prior to returning the non conforming product freight prepaid congatec AG will pay for...

Page 7: ...5 1 12 LPC Bus 27 5 1 13 I C Bus 27 5 1 14 SPI 27 5 1 15 Power Control 27 5 1 16 Power Management 29 6 Additional Features 30 6 1 Onboard Interfaces 30 6 1 1 Optional eMMC 4 5 30 6 1 2 Low Voltage Me...

Page 8: ...Management Submenu 77 10 4 16 CPU Configuration Submenu 77 10 4 16 1 Socket 0 CPU Information Submenu 78 10 4 16 2 CPU Thermal Configuration Submenu 79 10 4 17 PPM Configuration Submenu 79 10 4 18 The...

Page 9: ...ayPort DP Signal Descriptions 49 Table 19 CRT Signal Descriptions 51 Table 20 LVDS Signal Descriptions 51 Table 21 Serial ATA Signal Descriptions 52 Table 22 USB 2 0 Signal Descriptions 53 Table 23 US...

Page 10: ...assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Description GB Gigabyte GHz Gigah...

Page 11: ...le integrates all the core components and is mounted onto an application specific carrier board COM modules provide most of the functional requirements for any application These functions include but...

Page 12: ...l 18 24 bit Single Dual 18 24 bit Single Dual 18 24 bit DDI DP DP HDMI DVI DP DP HDMI DVI DP DP HDMI DVI DP DP HDMI DVI DP DP HDMI DVI DP DP HDMI DVI Memory DDR3L 1066 MT s dual channel 1066 MT s sing...

Page 13: ...HD Graphics Gen 7 full hardware acceleration for MPEG2 H 264 DirectX11 OCL 1 2 OGL 3 2 WMV9 and VC1 Dual simultaneous display support 2x DP DP HDMI DVI 1x LVDS 1x VGA Optional eDP interface NOTE 1 The...

Page 14: ...the conga TCA3 will not turn on See the Intel s Bay Trail datasheet for more information 2 2 Supported Operating Systems The conga TCA3 supports the following operating systems Microsoft Windows 7 8...

Page 15: ...Input Range Volts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 10...

Page 16: ...quency mode LFM with minimum core voltage during desktop idle The CPU was stressed to its maximum frequency S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to its maximum...

Page 17: ...3815 1 1 46 N A 0 35 0 53 0 59 0 18 047305 1 x 2 GB A 0 TA30R000 Windows 7 Intel Celeron J1900 4 2 00 2 42 0 40 1 33 1 33 0 18 Note With fast input voltage rise time the inrush current may exceed the...

Page 18: ...al variants Operation 40 to 85 C Storage 40 to 85 C Humidity Operation 10 to 90 Storage 5 to 95 Caution The above operating temperatures must be strictly adhered to at all times When using a congatec...

Page 19: ...DDI 1Dual Channel Non ECC DDR3L 1333 MT s NOTE 1 The Bay Trail SoC does not support mixed raw cards or mixed memory sizes Therefore use only symmetrical non ecc memory modules 2 The conga TCA3 o ers...

Page 20: ...entative and request the gap pad material manufacturer s specification Caution 1 The congatec heatspreaders cooling solutions are tested only within the commercial temperature range of 0 to 60 C There...

Page 23: ...CI Express The conga TCA3 offers five PCIe lanes on the A B connector The lanes support up to 5 GTps Gen 2 speed a 5 x1 link configuration a 3 x1 1 x2 link via a special customized BIOS firmware PCI E...

Page 24: ...0 resolutions at 60 Hz Note You can configure the optional second DP port only if LVDS is disabled in the BIOS setup menu 5 1 2 2 LVDS The conga TCA3 offers a single dual channel LVDS interface on the...

Page 25: ...Gb s legacy and AHCI mode 5 1 5 USB 2 0 The conga TCA3 offers eight USB 2 0 interfaces on connector rows A B Four of these ports are routed directly from the SoC to the A B connector The other four p...

Page 26: ...roller is connected to the Intel Bay Trail SoC through the fourth PCI Express lane 5 1 8 HDA Interface The conga TCA3 provides an interface that supports the connection of HDA audio codecs 5 1 9 UART...

Page 27: ...s implemented through the congatec board controller It provides a fast mode multi master I C bus at maximum I C bandwidth 5 1 14 SPI The conga TCA5 supports SPI interface This interface makes it possi...

Page 28: ...er supply In order to accomplish this the signal must be inverted with an inverter transistor that is supplied by standby voltage and is located on the carrier board PWRBTN When using ATX style power...

Page 29: ...s generate their own reset signals when the supply voltage exceeds a certain voltage threshold A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a ma...

Page 30: ...terface The memory interface supports 1 35 volts and unbuffered DDR3L SO DIMMs By leveraging this feature set the conga TCA3 offers a system optimized for lowest possible power consumption Note The co...

Page 31: ...nga TCA3 offers general purpose inputs and outputs for custom system design These GPIOs are multiplexed with SD signals and are controlled by the cBC 6 1 3 3 Fan Control The conga TCA3 has additional...

Page 32: ...anks to the I2 C host controller in the cBC the I2 C bus is multimaster capable and runs at fast mode 6 2 OEM BIOS Customization The conga TCA3 is equipped with congatec Embedded BIOS which is based o...

Page 33: ...later to replace add the OEM POST logo 6 2 4 OEM BIOS Code Data With the congatec embedded BIOS it is possible for system designers to add their own code to the BIOS POST process The congatec Embedded...

Page 34: ...ystem designer more flexibility when choosing the appropriate battery sub system For more information about this subject visit the congatec website and view the following documents congatec Battery Ma...

Page 35: ...pervisor supports Intel VT and is verified on all current congatec x86 hardware Note congatec supports RTS Hypervisor 7 1 2 Thermal Management ACPI is responsible for allowing the operating system to...

Page 36: ...systems support it S4_OS Hibernate Windows 7 Windows Vista Linux For more information about ACPI see section 10 4 8 ACPI Submenu Table 10 Wake Events The table below lists the events that wake the sy...

Page 37: ...may cause USB ports 4 7 ports routed via USB 2 0 hub to malfunction Bay Trail SoC COM Express Connector USB 2 0 Port2 USB 2 0 HUB USB 3 0 Port USB 2 0 Port0 SuperSpeed Port 0 USB 2 0 Port1 USB 2 0 Po...

Page 38: ...ll downs implemented by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer...

Page 39: ...MDI0 B13 SMB_CK A68 PCIE_TX0 B68 PCIE_RX0 A14 GBE0_CTREF B14 SMB_DAT A69 PCIE_TX0 B69 PCIE_RX0 A15 SUS_S3 B15 SMB_ALERT A70 GND FIXED B70 GND FIXED A16 SATA0_TX B16 SATA1_TX A71 LVDS_A0 B71 LVDS_B0 A1...

Page 40: ...D A96 TPM_PP B96 VGA_I2C_DAT A42 USB2 B42 USB3 A97 TYPE10 B97 SPI_CS A43 USB2 B43 USB3 A98 B98 RSVD A44 USB_2_3_OC B44 USB_0_1_OC A99 SER0_RX B99 RSVD A45 USB0 B45 USB1 A100 GND FIXED B100 GND FIXED A...

Page 41: ...GND D14 GND C69 PEG_RX5 D69 PEG_TX5 C15 DDI1_PAIR6 D15 DDI1_CTRLCLK_AUX C70 GND FIXED D70 GND FIXED C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX C71 PEG_RX6 D71 PEG_TX6 C17 RSVD D17 RSVD C72 PEG_RX6 D72 PEG_T...

Page 42: ...1 D42 DDI2_PAIR1 C97 RVSD D97 RSVD C43 DDI3_PAIR1 D43 DDI2_PAIR1 C98 PEG_RX14 D98 PEG_TX14 C44 DDI3_HPD D44 DDI2_HPD C99 PEG_RX14 D99 PEG_TX14 C45 RSVD D45 RSVD C100 GND FIXED D100 GND FIXED C46 DDI3_...

Page 43: ...tion Revision 2 0 PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 2 0 PCIE_RX4 PCIE_RX4 B55 B56 PCI Express ch...

Page 44: ...RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72...

Page 45: ...14 PEG_TX15 PEG_TX15 D52 D53 D55 D56 D58 D59 D61 D62 D65 D66 D68 D69 D71 D72 D74 D75 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential...

Page 46: ...I 3 3V PD 1M DDI1_CTRLCLK_AUX D15 Multiplexed with SDVO1_CTRLCLK DP1_AUX and HDMI1_CTRLCLK DP AUX function if DDI1_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLCLK if DDI1_DDC_AUX_SEL is pulled high I O...

Page 47: ..._LANE2 and TMDS3_DATA0 Multiplexed with DP3_LANE2 and TMDS3_DATA0 O PCIE Not supported DDI3_PAIR3 DDI3_PAIR3 C49 C50 Multiplexed with DP3_LANE3 and TMDS3_CLK Multiplexed with DP3_LANE3 and TMDS3_CLK O...

Page 48: ...2_PAIR3 and DDI2_PAIR3 O PCIE TMDS2_DATA0 TMDS2_DATA0 D46 D47 TMDS differential pair Multiplexed with DDI2_PAIR2 and DDI2_PAIR2 O PCIE TMDS2_DATA1 TMDS2_DATA1 D42 D43 TMDS differential pair Multiplexe...

Page 49: ...link for the transport of isochronous streams and secondary data Multiplexed with DDI1_PAIR2 and DDI1_PAIR2 O PCIE DP1_LANE1 DP1_LANE1 D29 D30 Uni directional main link for the transport of isochrono...

Page 50: ...O PCIE Not supported DP3_LANE2 DP3_LANE2 C46 C47 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR2 and DDI3_PAIR2 O PCIE Not supported D...

Page 51: ...DDC clock line I C port dedicated to identify VGA monitor capabilities I O OD 5V PU 4k02 3 3V VGA_I2C_DAT B96 DDC data line I O OD 5V PU 4k02 3 3V Table 20 LVDS Signal Descriptions Signal Pin Descrip...

Page 52: ...pair O SATA Supports Serial ATA II specification up to 3 Gb s SATA1_RX SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA Supports Serial ATA II specification up to 3 Gb s SA...

Page 53: ...wards compatible to USB 1 1 USB6 A36 USB Port 6 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB7 B37 USB Port 7 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB7...

Page 54: ...differential pairs for the Superspeed USB data path O Not supported USB_SSTX2 D9 O Not supported USB_SSRX3 C13 Additional receive signal differential pairs for the Superspeed USB data path I Not suppo...

Page 55: ...udio Sync This signal is a 48 kHz fixed rate sample sync to the codec s It is also used to encode the stream number O 3 3V AC 97 codecs are not supported AC HDA_BITCLK A32 Intel High Definition Audio...

Page 56: ...S flash O 3 3VSB SPI_CLK A94 Clock from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power source for carrier board SPI BIOS flash SPI_POWER shall be used to power SPI BIOS flash on t...

Page 57: ...ut to SD O 3 3V GPO1 B54 General purpose output pins Shared with SD_CMD Output from COM Express input to SD O 3 3V GPO2 B57 General purpose output pins Shared with SD_WP Output from COM Express input...

Page 58: ...as PS_ON may be used to enable the non standby power on a typical ATX power supply O 3 3VSB SUS_S4 A18 Indicates system is in Suspend to Disk state Active low output O 3 3VSB SUS_S5 A24 Indicates sys...

Page 59: ...efinition Signal Description Signal Pin Description I O Comment TYPE0 TYPE1 TYPE2 C54 C57 D57 The TYPE pins indicate to the Carrier Board the Pin out Type that is implemented on the module The pins ar...

Page 60: ...iptions Signal Pin Description I O PU PD Comment VCC_12V A104 A109 B104 B109 C104 C109 D104 D109 Primary power input 12V nominal All available VCC_12V pins on the connector s shall be used P VCC_5V_SB...

Page 61: ...is no connect HDMI DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU100k 3 3V DDI2_CTRLDATA_AUX is a boot strap signal see caution statement below Caution 1 The signals liste...

Page 62: ...I O space ranges seen by the processor are Device IO Address 8259 Master 20h 21h 24h 25h 28h 29h 2Ch 2Dh 30h 31h 34h 35h 38h 39h 3Ch 3Dh 8254s 40h 43h 50h 53h Ps2 Control 60h 64h NMI Controller 61h 6...

Page 63: ...03h PCI Express Root Port 3 00h 1Dh 00h EHCI USB 00h 1Fh 00h LPC Bridge to Intel Legacy Port 00h 1Fh 03h SMBus Port 03h 00h 00h PLX PE8605 PCI Express Bridge 04h 01h 00h PLX PCI Express Port 0 04h 02h...

Page 64: ...re virtual message based 2 Interrupt used by single function PCI Express devices INTA 3 Interrupt used by multifunction PCI Express devices INTB 4 Interrupt used by multifunction PCI Express devices I...

Page 65: ...device that should be used or an option to enter the BIOS setup program 10 2 Setup Menu and Navigation The congatec BIOS setup screen is composed of the menu bar left frame and right frame The menu ba...

Page 66: ...urn to the main setup screen by selecting the Main tab Feature Options Description Main BIOS Version No option Displays the main BIOS version OEM BIOS Version No option Displays the additional OEM BIO...

Page 67: ...rity Save Exit Watchdog Graphics Hardware Health Monitoring Trusted Computing RTC Wake Module Serial Ports Reserve Legacy Interrupt ACPI Super IO Intel R Smart Connect Technology Serial Port Console R...

Page 68: ...tchdog One time Trigger Disables watchdog after the first trigger Single Event Executes every stage once before the watchdog is disabled Repeated Event Executes the last stage repeatedly until reset N...

Page 69: ...ical but orderly operating system shutdown or restart Note In ACPI mode it is not possible for a Watchdog ACPI Event handler to directly restart or shutdown the operating system For this reason the co...

Page 70: ...EDID 1 Customized EDID 2 Customized EDID 3 Select a predefined LFP type or choose Auto to let the BIOS automatically detect and configure the attached LVDS panel Auto detection is performed by readin...

Page 71: ...cklight Delay No Delay 100ms Delay 250ms Delay 500ms Delay 1s Delay Set a delay to adjust the LVDS panel timings The congatec board controller will add the delay to the backlight signal coming from th...

Page 72: ...irmation Disabled Enabled Enable or disable user confirmation requests for certain transactions TPM State Disabled Enabled Enable or disable TPM chip Note The system may restart several times during P...

Page 73: ...device 10 4 8 ACPI Submenu Feature Options Description Enable ACPI Auto Configuration Disabled Enabled Enable or disable BIOS ACPI auto configuration Enable Hibernation Disabled Enabled Enable or disa...

Page 74: ...ce Enable Disable Enable or disable logical device Logical Device Settings No option Displays logical device settings Possible Use Automatic Settings IO 3F8 IRQ 3 4 5 7 9 10 11 12 DMA IO 2F8 IRQ 3 4 5...

Page 75: ...settings Possible Use Automatic Settings IO 60h IO 64h IRQ 1 Select configuration for PS2 10 4 14 Intel Smart Connect Technology Submenu Feature Options Description ISCT Support Disabled Enabled Enabl...

Page 76: ...ttings Submenu Opens console redirection configuration submenu Note The Serial Port Console Redirection can be only enabled if an external Super I O offering UARTs has been implemented on the carrier...

Page 77: ...0 Select the function key and keypad for Putty 10 4 15 2 Console Redirection Settings Out of Band Management Submenu Feature Options Description Terminal Type VT100 VT100 VT UTF8 ANSI Set the terminal...

Page 78: ...of adjacent cache lines Intel Virtualization Technology Disabled Enabled Enable or disable support for the Intel virtualization technology Power Technology Disable Energy Efficient Custom Configure t...

Page 79: ...state Report Disabled Enabled Enable or disable CPU state report to the operating system Enhanced CPU C state Disabled Enabled Enable or disable enhanced CPU C states Max CPU C state C7 C6 C1 Set the...

Page 80: ...isabled Enable or disable the onboard SATA controller SATA Test Mode Enabled Disabled Enable this feature for verification measurements only SATA Speed Support Gen1 Gen2 Displays the maximum SATA spee...

Page 81: ...on event timer PCI Express Dynamic Clock Gating Enabled Disabled Enable or disable dynamic clock gating 10 4 21 SCC Configuration Submenu Feature Options Description SCC Device Mode ACPI Mode PCI Mode...

Page 82: ...A palette registers snooping PERR Generation Disabled Enabled Enable or disable PCI device to generate PERR SERR Generation Disabled Enabled Enable or disable PCI device to generate SERR Above 4G Deco...

Page 83: ...Disabled Auto Force L0s Select the ASPM Level Disabled Disables ASPM Auto BIOS auto configure Force L0s Forces all links to L0s state Extended Synch Disabled Enabled Enable this feature to allow the...

Page 84: ...isable the Latency Tolerance Reporting LTR mechanism End End TLP Prefix Blocking Disabled Enabled If set to Enabled this function will block forwarding of TLPs containing End End TLP prefixes Target L...

Page 85: ...Gate A behavior Option ROM Messages Force BIOS Keep Current Enable or disable option ROM message INT19 Trap Response Immediate Postponed Select the BIOS reaction on INT19 trapping by option ROM Immed...

Page 86: ...is enabled the EHCI ownership change should be claimed by the EHCI operating system driver USB Mass Storage Driver Support Disabled Enabled Enable or disable mass storage driver support Device Reset...

Page 87: ...nable Disable Enable or disable AT platform Pre Boot Authentication PBA Intel AT Suspend Mode Enable Disable Enable or disable AT suspend mode 10 4 31 Intel Ethernet Connection I210 Submenu Feature Op...

Page 88: ...ers connected to the system 10 5 Chipset Setup Select the Boot tab from the setup menu to enter the Boot setup screen 10 5 1 North Bridge Submenu Feature Options Description Memory Information Total M...

Page 89: ...d write protection Generate EXCD0 1_PERST Disabled 1ms 5ms 10ms 50ms 100ms 150ms 200ms 250ms The COM Express EXCD0_PERST and EXCD1_PERST pins are driven low during POST for the set duration Isolate SM...

Page 90: ...controller Auto USB ports will initially function in USB 2 0 mode but the operating system driver can switch to USB 3 0 Smart Auto Identical to Auto except the BIOS will take over the operating system...

Page 91: ...e or disable PCIe port 0 Speed Auto Gen 2 Gen 1 Select PCIe speed on port 0 PCI Express Port 1 Disabled Enabled Enable or disable PCIe port 1 Speed Auto Gen 2 Gen 1 Select PCIe speed on port 1 PCI Exp...

Page 92: ...mputer Last State Restores the previous power state before power loss occurred Note If you want to use this feature chose an ATX type power supply AT Shutdown Mode System Reboot Hot S5 Select the beha...

Page 93: ...only lock if a user password is installed 10 8 Save Exit Menu Select the Save Exit tab from the setup menu with the Arrow keys to enter the Save Exit setup screen Feature Description Save Changes and...

Page 94: ...BIOS displays the BIOS project name and the revision code during POST and on the main setup screen The initial production BIOS for conga TCA3 is identified as TA31R1xx or TA32R1xx where TA31 is the B...

Page 95: ...ell for critical updates 11 2 1 Update from External Flash For instructions on how to update the BIOS from external flash refer to the AN7_External_BIOS_Update pdf application note on the congatec web...

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