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Copyright

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2018

congatec

AG

TR44m17

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Signal

Pin # Description

I/O

PU/PD Comment

DDI
DDI3_PAIR1-

C42
C43

Multiplexed with DP and TMDS.
Multiplexed with DP3_LANE1- and TMDS3_DATA1-.

O PCIE

DDI
DDI3_PAIR2-

C46
C47

Multiplexed with DP and TMDS.
Multiplexed with DP3_LANE2- and TMDS3_DATA0-.

O PCIE

DDI
DDI3_PAIR3-

C49
C50

Multiplexed with DP and TM.
Multiplexed with DP3_LANE3- and TMDS3_CLK-.

O PCIE

DDI3_HPD

C44

Multiplexed with DP3_HPD and HDMI3_HPD.

I 3.3V

PD 100K

DDI3_CTRL

C36

Multiplexed with and HDMI3_CTRLCLK.
DP AUX+ function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high

I/O PCIE
OD 3.3V

PD 100k

DDI3_CTRLDATA_AUX-

C37

Multiplexed with DP3_AUX- and HDMI3_CTRLDATA.
DP AUX- function if DDI3_DDC_AUX_SEL is no connect.
HDMI/DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high.

I/O PCIE
I/OD 3.3V

PU 100k

DDI3_DDC_AUX_SEL

C38

Selects the function of DDI3_CTRL and DDI3_CTRLDATA_AUX-.
This pin shall have a IM pull-down to logic ground on the module. If this input
is floating, the AUX pair is used for the DP AUX+/- signals. If pulled-high, the
AUX pair contains the CTRLCLK and CTRLDATA signals

I 3.3V

PD 1M

Note

The DDI interfaces support dual-mode DisplayPort. To support HDMI/DVI, an external level shifter (PTN3360D) should be implemented on

the user’s carrier board.

Table 31

HDMI/DVI Signal Descriptions

Signal

Pin # Description

I/O

PU/PD

Comment

TMD
TMDS1_CLK -

D36
D37

HDMI/DVI TMDS Clock output differential pair.
Multiplexed with DDI and DDI1_PAIR3-.

O PCIE

TMDS
TMDS1_DATA0-

D32
D33

HDMI/DVI TMDS differential pair.
Multiplexed with DDI and DDI1_PAIR2-.

O PCIE

TMDS
TMDS1_DATA1-

D29
D30

HDMI/DVI TMDS differential pair.
Multiplexed with DDI and DDI1_PAIR1-.

O PCIE

TMDS
TMDS1_DATA2-

D26
D27

HDMI/DVI TMDS differential pair.
Multiplexed with DDI and DDI1_PAIR0-.

O PCIE

HDMI1_HPD

C24

HDMI/DVI Hot-plug detect. Multiplexed with DDI1_HPD.

I PCIE

PD 100K

HDMI1_CTRLCLK

D15

HDMI/DVI I

2

C Control Clock. Multiplexed with DDI1_CTRL

OD 3.3V

PD 100K

2.2k to 3.3V Pull-up must be implemented on
the carrier board.

HDMI1_CTRLDATA

D16

HDMI/DVI I

2

C Control Data

Multiplexed with DDI1_CTRLDATA_AUX-

I/OD 3.3V PU 100K

3.3V

2.2k to 3.3V Pull-up must be implemented on
the carrier board.

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Summary of Contents for 041600

Page 1: ...Copyright 2018 congatec AG TR44m17 1 65 COM Express conga TR4 COM Express Type 6 Basic module based on 4th Generation AMD Embedded V and R Series SoC User s Guide Revision 1 7...

Page 2: ...supported memory in table 4 Added information about the new industrial variant in table 3 and 7 1 3 2019 07 30 BEU Updated note in section 4 Cooling Solutions Changed number of supported USB 3 1 Gen...

Page 3: ...technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any incidental consequential s...

Page 4: ...that should be observed Copyright Notice Copyright 2018 congatec AG All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission f...

Page 5: ...non conforming product freight prepaid congatec AG will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair w...

Page 6: ...ation utilities and drivers which have been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support co...

Page 7: ...5 1 13 Power Management 30 5 2 Secondary Connector Rows C and D 31 5 2 1 PCI Express Graphics PEG 31 5 2 2 Digital Display Interface DDI 31 6 Additional Features 32 6 1 congatec Board Controller cBC 3...

Page 8: ...Copyright 2018 congatec AG TR44m17 8 65 10 BIOS Setup Description 64 10 1 Navigating the BIOS Setup Menu 64 10 2 BIOS Versions 64 10 3 Updating the BIOS 65 10 4 Supported Flash Devices 65...

Page 9: ...s Signal Descriptions general purpose 45 Table 18 Gigabit Ethernet Signal Descriptions 46 Table 19 LVDS Signal Descriptions 47 Table 20 UART Interface Signal Descriptions 47 Table 21 SPI BIOS Flash In...

Page 10: ...ion and comply with COM Express 3 0 specification They are equipped with two high performance connectors that ensure stable data throughput and support high bandwidth networking The COM computer on mo...

Page 11: ...e dual rank Graphics Engine AMD Radeon Vega 11 AMD Radeon Vega 8 AMD Radeon Vega 8 AMD Radeon Vega 3 GPU Clock Speed 1300 MHz 11 Compute Units 1300 MHz 8 Compute Units 1100 MHz 8 Compute Units 1000 MH...

Page 12: ...GPU Clock Speed 1300 MHz 8 Compute Units 1200 MHz 3 Compute Units 1000 MHz 3 Compute Units PCIe 1x PCIe Gen 3 x8 x4 4x PCIe Gen 3 x4 x2 x1 4x PCIe Gen 2 x1 1x PCIe Gen 3 x4 3x PCIe Gen 3 x1 4x PCIe G...

Page 13: ...W encode and decode 10b HEVC and VP9 decode MS compliant JPEG encode and decode Up to four independent displays three in R Series 1x PCIe Gen 3 x8 x4 Only x4 in R Series 1x LVDS default or 1x eDP opti...

Page 14: ...4 after installing Microsoft Windows Operating System congatec AG recommends the installation of AMD catalyst driver 2 3 Mechanical Dimensions 95 0 mm x 125 0 mm 3 74 x 4 92 Height approximately 18 or...

Page 15: ...inout Type 6 dual connector 440 pins Table 5 Electrical Characteristics Power Rail Module Pin Current Capability Amps Nominal Input Volts Input Range Volts Derated Input Volts Max Input Ripple 10Hz to...

Page 16: ...ment Description The power consumption values were recorded during the following system states System State Description Comment S0 Minimum value Lowest frequency mode LFM with minimum core voltage dur...

Page 17: ...3 47 0 17 0 08 041620 2x4 GB DDR4 2400 C 0 TR44R205 Windows 10 R1606G 2 2 6 3 5 0 38 2 22 2 57 0 16 0 08 041621 2x4 GB DDR4 2400 C 0 TR44R205 Windows 10 R1505G 2 2 4 3 3 0 37 2 09 2 19 0 16 0 08 Note...

Page 18: ...al variants Operation 40 to 85 C Storage 40 to 85 C Humidity Operation 10 to 90 Storage 5 to 95 Caution The above operating temperatures must be strictly adhered to at all times When using a congatec...

Page 19: ...A I F USB Port 0 4 SATA Port 0 SATA Port 2 SATA Port 1 SATA Port 3 GPIOs SM Bus I2C Bus Serial Port 1 0 FAN Control VGA USB SS Port 0 USB SS Port 2 DDI 1 DDI 2 DDI 3 N A in R Series PEG x4 USB 3 1 Gen...

Page 20: ...d to For more information about this subject contact your local congatec sales representative and request the gap pad material manufacturer s specification Caution 1 The congatec heatspreaders cooling...

Page 21: ...Copyright 2018 congatec AG TR44m17 21 65 4 1 CSA Dimensions 96 6 95 125 20 21 29 Threaded standoff for threaded version or non threaded standoff for borehole version...

Page 22: ...Copyright 2018 congatec AG TR44m17 22 65 4 2 CSP Dimensions Threaded standoff for threaded version or non threaded standoff for borehole version 95 125 20 28...

Page 23: ...Copyright 2018 congatec AG TR44m17 23 65 4 3 Heatspreader Dimensions 87 117 11 4 0 6 Threaded standoff for threaded version or non threaded standoff for borehole version...

Page 24: ...signals for eight USB 2 0 ports The signals for USB 2 0 ports 0 4 are routed from the SoC The signals for USB 2 0 ports 5 7 are routed from a USB hub on the module The USB 2 0 signals can be combined...

Page 25: ...he GBE0_LINK100 and GBE0_LINK1000 signals on the conga TR4 Network Booting PXE is not possible with D Link Switch Model No DGS 1008D 5 1 5 LPC Bus conga TR4 offers the Low Pin Count LPC bus via the in...

Page 26: ...upports Single or dual channel LVDS color depths of 18 bpp or 24 bpp VESA and JEIDA color mappings Resolution up to 1920x1200 60 Hz in in dual LVDS bus mode color depth 24 bpp Gen 3 Port 1 AMD SoC V S...

Page 27: ...nga TR4 offers signals for two UART interfaces routed from the SoC by default Optionally the signals can be routed from the congatec Board Controller cBC instead Two TTL compatible two wire ports are...

Page 28: ...cks are stable Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems It is a good design practice to delay the PWR_OK signal a little typically 100ms after all ca...

Page 29: ...nly around 0 8V when the 12V is applied to the module Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving Therefore congatec recommends driving t...

Page 30: ...ining necessary voltages are internally generated on the module using onboard voltage regulators A carrier board designer should be aware of the following important information when designing a power...

Page 31: ...DI2 is multiplexed with a USB 3 1 Gen 2 port See section section 7 4 USB Host Controller for more information DDI3 N A in R Series is multiplexed with a USB 3 1 Gen 2 port See section section 7 4 USB...

Page 32: ...nctions to further improve system management One of these signals is an output signal called FAN_PWMOUT that allows system fan control using a PWM Pulse Width Modulation output Additionally there is a...

Page 33: ...on the congatec website at www congatec com or contact technical support The customization features supported are described in the following sections 6 2 1 OEM Default Settings This feature allows sy...

Page 34: ...2 5 OEM DXE Driver This feature allows designers to add their own UEFI DXE driver to the congatec embedded BIOS Contact congatec technical support for more information on how to add an OEM DXE driver...

Page 35: ...Win64 Win CE Linux The architecture of the CGOS API driver provides the ability to write application software that runs unmodified on all congatec CPU modules All the hardware related code is contain...

Page 36: ...in the System Resources section of this user s guide as well as some of the setup nodes found in the BIOS Setup Program description section 7 1 AMD Processor Features Zen microarchitecture Fetch Four...

Page 37: ...cool the thermal zone without having to reduce the overall system performance Use the active cooling trip point setup node in the BIOS setup program to determine the temperature threshold that the op...

Page 38: ...apabilities of a PCI device using Windows Device Manager configuration options for this device OR set Resume On PME to Enabled in the Power setup menu USB Mouse Keyboard Event When Standby mode is set...

Page 39: ...ured in the BIOS setup menu to operate in Gen 1 mode Before changing the setting to Gen 2 ensure the carrier board is designed for Gen 2 operation For USB 3 1 Gen 2 design considerations contact conga...

Page 40: ...t present the signal is asserted when at a high voltage level Table 11 Signal Tables Terminology Descriptions Term Description I Input Pin O Output Pin OC Open Collector OD Open Drain PU Implemented p...

Page 41: ...A0 B71 LVDS_B0 A17 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX...

Page 42: ...B105 VCC_12V A51 GND FIXED B51 GND FIXED A106 VCC_12V B106 VCC_12V A52 PCIE_TX5 B52 PCIE_RX5 A107 VCC_12V B107 VCC_12V A53 PCIE_TX5 B53 PCIE_RX5 A108 VCC_12V B108 VCC_12V A54 GPI0 B54 GPO1 A109 VCC_1...

Page 43: ...0_RX SATA0_RX A19 A20 Serial ATA channel 0 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 Only two SATA ports can be set to active via BIOS setup SATA0_TX SATA0_...

Page 44: ...the module USB6 A36 USB Port 6 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 Routed from a USB hub on the module USB7 B37 USB Port 7 data or D I O USB 2 0 compliant Backwards compati...

Page 45: ...xpress Base Specification Revision 3 0 PCIE_RX3 PCIE_RX3 B58 B59 PCI Express channel 3 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_TX3 PCIE_TX3 A58...

Page 46: ...w O 3 3VSB GBE0_LINK100 A4 Gigabit Ethernet Controller 0 100Mbit sec link indicator active low O 3 3VSB GBE0_LINK1000 A5 Gigabit Ethernet Controller 0 1000Mbit sec link indicator active low O 3 3VSB G...

Page 47: ...3V PD 10K LVDS_BKLT_EN B79 LVDS panel backlight enable O 3 3V PD 10K LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3 3V LVDS_I2C_CK A83 DDC lines used for flat panel detection and cont...

Page 48: ...ins O 3 3V GPI0 A54 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI1 A63 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI2...

Page 49: ...M state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON may be used to enable the non standby power on a typical ATX power supply O 3 3VSB SUS_S4 A18 Indicates sy...

Page 50: ...Y is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in the system design P VCC_...

Page 51: ...70 GND FIXED C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX C71 PEG_RX6 D71 PEG_TX6 C17 RSVD D17 RSVD C72 PEG_RX6 D72 PEG_TX6 C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7...

Page 52: ...9 PEG_RX14 D99 PEG_TX14 C45 RSVD D45 RSVD C100 GND FIXED D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD D48...

Page 53: ...path O USB_SSTX2 D9 O USB_SSRX3 C13 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX3 C12 I USB_SSTX3 D13 Additional transmit signal differential pairs for the...

Page 54: ...PEG_RX5 PEG_RX5 PEG_RX6 PEG_RX6 PEG_RX7 PEG_RX7 PEG_RX8 PEG_RX8 PEG_RX9 PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55...

Page 55: ...2 PEG_TX12 PEG_TX13 PEG_TX13 PEG_TX14 PEG_TX14 PEG_TX15 PEG_TX15 D52 D53 D55 D56 D58 D59 D61 D62 D65 D66 D68 D69 D71 D72 D74 D75 D78 D79 D81 D82 D85 D86 D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI E...

Page 56: ...AUX signals If pulled high the AUX pair contains the CTRLCLK and CTRLDATA signals I 3 3V PD 1M DDI2_PAIR0 DDI2_PAIR0 D39 D40 Multiplexed with DP2_LANE0 and TMDS2_DATA2 Multiplexed with DP2_LANE0 and...

Page 57: ...f this input is floating the AUX pair is used for the DP AUX signals If pulled high the AUX pair contains the CTRLCLK and CTRLDATA signals I 3 3V PD 1M Note The DDI interfaces support dual mode Displa...

Page 58: ...U 100K 3 3V 2 2k to 3 3V Pull up must be implemented on the carrier board TMDS3_CLK TMDS3_CLK C49 C50 HDMI DVI TMDS Clock output differential pair Multiplexed with DDI3_PAIR3 and DDI3_PAIR3 O PCIE TMD...

Page 59: ...tional main link for the transport of isochronous streams and secondary data Multiplexed with DDI2_PAIR1 and DDI2_PAIR1 O PCIE DP2_LANE0 DP2_LANE0 D39 D40 Uni directional main link for the transport o...

Page 60: ...logic may also implement a fault indicator such as an LED TYPE10 A97 Dual use pin Indicates to the carrier board that a Type 10 module is installed Indicates to the carrier that a Rev 1 0 2 0 module i...

Page 61: ...On the conga TR4 the following I O address ranges are sent to the LPC Bus SupperIO Index 2Eh 2Fh SerialPort0 3F8h 3FFh SerialPort1 2F8h 2FFh SerialPort2 3F0h 3F7h SerialPort3 3E0h 3E7h SerialPort4 2F...

Page 62: ...A 00h 08h 02h 0x15DC Internal PCIe GPP Bridge 0 to Bus B 00h 14h 00h 0x790B SMBus Controller 00h 14h 03h 0x790E LPC Bridge 00h 18h 00h 0x15E8 Data Fabric 00h 18h 01h 0x15E9 Data Fabric 00h 18h 02h 0x...

Page 63: ...Ports may only be visible if the PCI Express Graphics Port is set to Enabled in BIOS setup and a device is attached to the corresponding PCI Express port on the carrier board 3 The above table repres...

Page 64: ...ote If you do not have access to the restricted area of the congatec website contact your local congatec sales representative 10 1 Navigating the BIOS Setup Menu The BIOS setup menu shows the features...

Page 65: ...ser s guide for the congatec System Utility CGUTLm1x pdf on the congatec website at www congatec com Note 1 Deprecated Caution The DOS command line tool is not officially supported by congatec and the...

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