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updated as required.
6.
Clock switch is complete.
HFINTOSC
LFINTOSC
IRCF = 0
IRCF
≠
0
HFINTOSC
启动时间
两个周期后切换
IRCF
SYSCLK
Figure 5-2. Switch from Slow Clock to Fast Clock Diagram
LFINTOSC
HFINTOSC
IRCF = 0
IRCF
≠
0
IRCF
SYSCLK
LFINTOSC
启动时间
两个周期后切换
Figure 5-3. Switch from Fast Clock to Slow Clock Diagram
5.2
Clock Switching
The System Clock Select bit (SCS) of the OSCCON register is operated via software, and the system clock
source can be switched between the external and internal clock sources.
5.2.1
System Clock Select Bit (SCS)
The System Clock Select bit(SCS) of the OSCCON register selects the system clock sourcethat is used for
the CPU and peripherals.
When the System Clock Select bit (SCS) of the OSCCON register is 0, the system clock source is
determined by configuration of the FOSC<2:0> bit in the Configuration Word register (UCFG0).
When the System Clock Select bit (SCS) of the OSCCON register is 1, the system clock source is
selected according to the internal oscillator frequency selected by the IRCF<2:0> bit of the OSCCON
register. After aReset, SCS is always cleared.
Note:
Any clock switching caused by the hardware (possibly from Two-Speed Start-up or Fail-Safe Clock Monitor)
will not update the SCS bit of the OSCCON register. The user should monitor the OSTS bit of the OSCCON
