CMOSTEK CMT2189C User Manualline Download Page 18

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AN202

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4.1.2

Bank1 SFR

Table 4-2. Bank1 Register List

ADDR

Name

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

POR reset

INDF

Access the data memory by using the content of FSR (non physical registers)

x xx x x xx x

OPTION

/PAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

PCL

Program Counter<7:0>

0000 0000

STATUS

PAGE

/TF

/PF

- - 0 1 1 x x x

FSR

Indirect Data Memory Address Pointer

TRISA

TRISA<7:6>

TRISA<4:0>

11x1 1111

- - - - - - - -

TRISC

TRISC<7:0>

1111 1111

- - - - - - - -

PCLATH

Program Counter<13:8>

- - - 0 0 0 0 0

INTCON

GIE

PEIE

T0IE

INTE

PAIE

T0IF

INTF

PAIF

0000 0000

PIE1

EEIE

CKMEAIE

C2IE

C1IE

OSFIE

TMR2IE

00 -0 0 00 -

- - - - - - - -

PCON

/POR

/BOR

- - - - - - q q

OSCCON

LFMOD

IRCF[2:0]

OSTS

HTS

LTS

SCS

0101 x000

- - - - - - - -

0000 0000

PR2

PR2[7:0], Timer2 period register

1111 1111

- - - - - - - -

WPUA

WPUA<7:6>

WPUA<4:0>

11-1 1111

IOCA

IOCA<7:0>

- - - - - - - -

VRCON

VREN

VRR

VR<3:0>

0- 0- 00 00

EEDAT

EEDAT<7:0>

0000 0000

EEADR

EEADR<7:0>

0000 0000

EECON1

WREN3

WREN2

WRERR

WREN1

- - 0 0 x 0 - 0

EECON2

- - - - - - - 0

- - - - - - - -

A0-BF

Bank1's SRAM, which is the general RAM of 32Bytes.

x xx x x xx x

C0-EF

- - - - - - - -

F0-FF

SRAM. Access Bank0

’s 0x70

～

0x7F.

x xx x x xx x

Note:

1. INDF is not a physical register.

2. The gray part is unimplemented, please do not access.

3. "-" indicates that it is unimplemented; the unimplemented register bits can not be used or written as1. It is

Summary of Contents for CMT2189C

Page 1: ...roduct series include the short range wireless communication chips such as transmitter receiver transceiver SoC and so on The part numbers covered by this document are as shown below Table1 Part Numbe...

Page 2: ...mission Process 14 3 Program Memory 16 4 Special Function Register SFR 17 4 1 Address Mapping 17 4 1 1 Bank0 SFR 17 4 1 2 Bank1 SFR 18 4 1 3 TMR0 Addr 0x01 19 4 1 4 STATUS Addr 0x03 19 4 1 5 PORTA Add...

Page 3: ...lect Bit IRCF 40 5 1 3 Clock Switch Timing of HFINTOSC and LFINTOSC 40 5 2 Clock Switching 41 5 2 1 System Clock Select Bit SCS 41 5 2 2 Oscillator Start up Timeout Status OSTS Bit 42 5 3 Two Speed Cl...

Page 4: ...4 Interrupt Mode 60 14 1 INT Interrupt 60 14 2 PORTA Level Change Interrupt 61 14 3 Interrupt Response 61 14 4 Context Saving During Interrupts 63 15 MCU Sleep Saving Mode 64 15 1 Wake up Mode 64 15 2...

Page 5: ...ital Logic EEPROM Loop Filter Modulator Ramp Control VCO XOSC AVDD GND XTAL RFCLK RFDAT PAP POR Bandgap PA CPU Program ROM 2K 14Bit Data EEPROM 256 8Bit TMR WDT IO CMP RSTC OST PWRT BOOT CLKC IRCCK SF...

Page 6: ...PAN Analog O Chip PA output 5 PC2 RFCLK Digital IO PC2 General IO RFCLK RF communication TWI bus clock line CLK internal pull up 6 PA5 MCLRB Digital I PA5 Only as input support IOC MCLRB External rese...

Page 7: ...n TWI bus data line DAT and also data transmitting pin internal pull down 13 GND Digital I Chip power supply ground 14 XTAL Analog I RF part crystal oscillator input Note The two comparators are integ...

Page 8: ...RFDAT to control the PA transmitting In the transmitting process if the time RFDAT holds a low level is longer than tSTOP setting time TSTOP is not unique and can be selected the specifics refer to RF...

Page 9: ...MT2119A It supports any frequency of Sub G ranging from 240MHz 960MHz and it also uses the TWI bus configuration interface Through the TWI interface users can allow CMT2189C to change the frequency fr...

Page 10: ...e exp file as shown below Figure 2 3 Export the parameter file Configure the generation parameters to the RF of CMT2189C according to the software lookup mode and then control the transmission accordi...

Page 11: ...0 ns DATA Setup Time tDS From DATA change to CLK falling edge 20 ns DATA Hold Time tDH From CLK falling edge to DATA change 200 ns tDS tDH tCH tCL RFCLK RFDAT Figure 2 4 TWI Timing Diagram RFCLK RFDAT...

Page 12: ...m is the actual read value 2 5 TWI Timing Enter and Exit In the TWI bus RFDAT is the data line of the TWI and it is also the data line of Tx When the RFDAT edge changes in order to distinguish between...

Page 13: ...onfiguration process is as follows TWI_RST SOFT_RST wait 1 ms before moving to Step 3 TWI_WRREG 0x02 0x78 1 TWI_WRREG 0x2F 0x80 2 TWI_WRREG 0x35 0xCA 3 TWI_WRREG 0x36 0xEB 4 TWI_WRREG 0x37 0x37 5 TWI_...

Page 14: ...nfigure all the registers that need to be When the user needs to do a read operation to confirm whether the write operation is correct the read operation is also indirect similar to the Step6 process...

Page 15: ...T 0 Wait for tSTOP Figure 2 11 Only Execute Configuration Parameters Once But this method is unable to achieve the low power consumption because users trigger the RF internal register to save temporar...

Page 16: ...UCFGx and factory configuration banks FCFGx the total is 64 Words They are made up of EEPROM Among them the 0 0x7FF is the main program bank the 0x800 0x1FFF is unimplemented bank which isreserved Th...

Page 17: ...ORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 00x0 0000 6 7 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0000 0000 8 9 A PCLATH Program Counter 13 8 0 0000 B INTCON GIE PEIE T0IE INTE PAIE T0IF INTF PAIF 0000 0000 C...

Page 18: ...E T0IF INTF PAIF 0000 0000 8C PIE1 EEIE CKMEAIE C2IE C1IE OSFIE TMR2IE 00 0 000 8D 8E PCON POR BOR q q 8F OSCCON LFMOD IRCF 2 0 OSTS HTS LTS SCS 0101 x000 90 91 0000 0000 92 PR2 PR2 7 0 Timer2 period...

Page 19: ...7Fh 1 BANK1 80h FFh 4 TF Time out bit 1 After power up CLRWDT instruction or SLEEP instruction 0 A WDT time out occured 3 PF Power down bit 1 After power up or by the CLRWDT instruction 0 By executat...

Page 20: ...set to 1 or cleaned according to the device logic Therefore the result of an instruction with the Status register as destination may be different than intended 2 It is suggested that only using the BC...

Page 21: ...et 0 0 0 0 0 0 0 0 Type RW RW RW RW RW RW RW RW Table 4 12 INTCON Bit Function Description Bit Name Function 7 PC7 PORTC7 data 6 PC6 PORTC6 data 5 PC5 PORTC5 data 4 PC4 PORTC4 data 3 PC3 PORTC3 data 2...

Page 22: ...one or more ports of PORTA 7 0 have changed state must be cleared in software 0 None of the PORTA 7 0 have changed state Bit Name Function 7 EEIF EEPROM Write OperationInterrupt Flag bit 1 The EE writ...

Page 23: ...imer2 to PR2 Match Interrupt Fag bit 1 Timer2 to PR2 match occurred must be cleared in software 0 Timer2 to PR2 match has not occurred 0 Reserved bit can not be written as 1 Bit Name Function 7 Reserv...

Page 24: ...er2 is off 1 0 T2CKPS 1 0 Timer2 Clock Prescale Select bits 00 1 1 Prescaler is 1 01 1 4 Prescaler is 4 1x 1 16 Prescaler is 16 Bit Name Function 7 5 Reserved bits read as 0 4 1 WDTPS 3 0 Watchdog Tim...

Page 25: ...IN C2VIN When C2INV 1 1 C2VIN C2VIN 0 C2V IN C2VIN 6 C1OUT Comparator1Outputbit When C1INV 0 1 C1VIN C1VIN 0 C1V IN C1VIN When C1INV 1 1 C1VIN C1VIN 0 C1V IN C1VIN 5 C2INV Comparator2 Output Inversio...

Page 26: ...omparators 010 Four inputs multiplexed to twocomparators 011 Two common reference comparators 100 Two independent comparators 101 One independent comparator 110 Two common reference comparatorswith ou...

Page 27: ...1 1 1 1 111 Type RW RW RW RW RW RW Table 4 30 OPTION Bit Function Description 2 CKMAVG Measurement average mode of fast clock measuring slowclock period 1 Open the average mode Automatically measure a...

Page 28: ...of PA2 INT pin 5 T0CS Timer0 Clock Source Select bit 1 Transition on PA2 T0CKI bit 0 Internal instruction cycle clock FOSC 2 4 T0SE Timer0 Source Edge Select bit 1 Increment on high to low transition...

Page 29: ...ORTA 4 0 port direction Control bits 1 Input 0 Output Bit Name Function 7 0 TRISC 7 0 PORTC 7 0 port direction Control bits 1 Input 0 Output Bit Name Function 7 EEIE EEPROM Write Complete Interrupt En...

Page 30: ...cillator fail interrupt 0 Disable the oscillator fail interrupt 1 TMR2IE Timer2 to PR2 Match Interrupt Enable bit 1 Enable 0 Disable Bit Name Function 1 POR Power onReset Status bit active low 0 A Pow...

Page 31: ...00KHz 001 250KHz 000 32KHz LFINTOSC 3 OSTS Oscillator Start up Timeout Status bit 1 Device is running from the external system clock defined by the FOSC 2 0 0 Device is running from the internal oscil...

Page 32: ...AN202 V1 0 Page 32 73 www cmostek com...

Page 33: ...VRCON VREN VRR VR 3 0 Reset 0 0 0 Type RW RW RW Table 4 48 VRCONBit Function Description Bit Name Function 7 6 WPUA 7 6 PORTA Weak Pull up Enable bit 1 Enable 0 Disable 4 0 WPUA 4 0 PORTA Weak Pull up...

Page 34: ...cription 3 0 VR 4 0 CVref Value Select Control bit When VRR 1 CVref VR 4 0 24 VDD When VRR 0 CVref VDD 4 VR 4 0 32 VDD Bit Name Function 5 4 2 WREN 2 0 EEPROM Write Enable bit 111 Allow write to the d...

Page 35: ...EEPROM Write Control bit Read operation 1 Data EEPROM is in the programming cycle 0 Data EEPROM is not in the programming cycle Write operation 1 Initiates a data EEPROM programming cycle 0 No functi...

Page 36: ...ode PA6 PA7 connects the high speed crystal oscillator 010 External clock mode PA6 is the IO pin PA7 is connected to the clock input 011 INTOSC mode PA6 output the 2 frequency division of the system c...

Page 37: ...tion with the PCL register as the destination simultaneously causes the Program Counter PC 10 8 bits to be replaced by the contents of PCLATH register This allows the entire contents of the program co...

Page 38: ...generate an indirect addressing and the addressable range is 0 255 Any instruction that uses the INDF register is actually access to the unit that the file selection register FSR points to Reading th...

Page 39: ...ariety of frequency clock sources The prescaler ratio of the system clock source can be controlled by the IRCF 2 0 bit in the OPTION register Note The watchdog the system clock source IRCF 000 and the...

Page 40: ...s internal oscillator frequency select bit IRCF 2 0 is used to select the frequency output of the internal oscillator Select one of the following eight frequencies via the software 16MHz 8MHz 4MHz Def...

Page 41: ...lock Select bit SCS of the OSCCON register selects the system clock sourcethat is used for the CPU and peripherals When the System Clock Select bit SCS of the OSCCON register is 0 the system clock sou...

Page 42: ...uction will abort the oscillator start up time and clear the OSTS bit of the OSCCON register When the oscillator module is configured as LP mode or XT mode enable the Oscillator Start upTimer OST See...

Page 43: ...expired FSCM can be enabled by setting the FCMEN bit in the Configuration Word register UCFG1 to 1 FSCM can be used for all external oscillator modes LP XT and EC LP XT EC Q Q SET CLR S R LFINTOSC 32...

Page 44: ...N After the OST is timeout the fail safe condition is cleared and the device will operate with the external clock source The fail safe condition must be cleared before clearing the OSFIF flag bit 5 4...

Page 45: ...t Reset BOR Error instruction Reset When WDT is used as a timer it can wake up MCU from Sleep The MCU continues to run after Wake up from Sleep while in normal operation WDT watchdog is timeout and re...

Page 46: ...se the following circuit VDD MCLRB 100R 1K 0 1uF Figure 6 2 External Reset Reference Circuit Diagram The chip s CONFIG OPTION register UCFG0 has a MCLRE Enable bit When this bit is 0 the reset signal...

Page 47: ...rated by the BOR circuit the VDD voltage must hold for more than 100us at the VSS level 6 5 Error Instruction Reset When the instruction register of CPU obtains the undefined instruction the system wi...

Page 48: ...s 2 The TBOR time is about 157us 3 After the voltage is restored to normal the internal reset will not be released immediately but wait for about 8ms Table 6 1 Timeout in aVariety of Cases Oscillator...

Page 49: ...k com Table 6 2 STATUS PCON Bit and Significance U No change X Unknown POR BOR TO PD Condition 0 X 1 1 POR U 0 1 1 BOR U U 0 U WDT Reset U U 0 0 WDT Wake up U U U U MCLR Reset during normal operation...

Page 50: ...POR or BOR inserting a status the unit of EEPROM is mapped into a configuration register The address of EEPROM starts from 2000H The system reset is released until the end of the BOOT as shown in Figu...

Page 51: ...ned by the BOOT during the power start up process or it can be written through the external serial port Clearing the watchdog instruction CLRWDT and SLEEP will clear the watchdog counter In the case o...

Page 52: ...the value of PSA is changed the hardware will automatically clear the prescaler WDT Set flag bit T0IF On overflow PSA WDTPS 3 0 16 bit Prescaler 8bit WDT Time out T0CKI T0SE T0CS WDTE 32K INTOSC 8 bit...

Page 53: ...rite operation to the TMR0 register will clear the prescaler circuit 2 When the prescaler circuit is assigned to WDT one CLRWDT instruction can clear the prescaler circuit 3 The prescaler circuit can...

Page 54: ...pt cannot wake up the CPUfrom Sleep since the timer is shut off during Sleep 9 3 3 Drive Timer0 with an External Clock In the counter mode the synchronization between T0CKI pin input and Timer0 regist...

Page 55: ...nstantly compared to determine when to match TMR2 will increase from 00h until it matches PR2 The following two cases will occur when matching TMR2 is reset to 0x00 on the next increment cycle Timer2...

Page 56: ...y the T2CKPS bit of the T2CON register 4 The Timer2 postscaler is controlled by the TOUTPS bit of the T2CON register 5 The prescaler counter and postscaler counter will be cleared when the following r...

Page 57: ...ON0 register Because the functional pins are used in the RF serial control bus there are only two statuses as follows Comparator Reset After POR CM 2 0 0b000 Off Off C1IN C1IN C2IN C2IN A A A A Compar...

Page 58: ...read or write Two times 0xAA is written for a certain unit of EEPROM that is not used and the subsequent program no longer operates on this unit Such as Programming data EEPROM steps In order to read...

Page 59: ...ment accuracy it is suggested that IRCF is set to 111 and SCS is set to 1 and the system clock of 16M is selected 2 Set T2CON 2 to 1 enable TIMER2 3 If selecting the average of the four times set MSCK...

Page 60: ...interrupt flag bit INT pin interrupt PORTA change interrupt Timer0 overflow interrupt PIR1 includes the Peripheral Interrupt Flag bit PIE1 includes its corresponding Interrupt Enable bit 14 1 INT Int...

Page 61: ...gured as an analog input is always read to 0 2 When initializing the level change interrupt first configure it as a digital input IO and set the corresponding IOCA to 1 and then read the PORTA 3 When...

Page 62: ...2 IOC RA3 IOCA3 IOC RA4 IOCA4 IOC RA5 IOCA5 IOC RA6 IOCA6 IOC RA7 IOCA7 TMR2IF TMR2IE EEIF EEIE CKMEAIF CKMEIE C1IF C1IE C2IF C2IE OSFIF OSFIE PEIE T0IF T0IE INTF INTE RAIF RAIE GIE Wakeup If in sleep...

Page 63: ...ed on the stack In general users may wish to savethe key register value on the stack such as W STATUS register and so on These must be implemented insoftware The temporary registers W_TEMP and STATUS_...

Page 64: ...parator module is closed 15 1 Wake up Mode The following events can wake up the chip There is an external reset on the MCLR pin WDT is timeout There is the interrupt on the PA2 INT pin There is the PO...

Page 65: ...output register All operations follow the read modify write micro process namely the data is read and then is modified and then is written to the output register When MCLRE is 1 the value read from PO...

Page 66: ...it Reading the PORTA once can end any status of error matching and clear the PAIF bit The last read value kept in the data register will not be affected by MCLR or BOR As long as the error matching st...

Page 67: ...RD IOCA Interrupt On Change D Q Q _ D Q Q _ RD PORTA Qn T0CKI PA2 Only D CLK Q Q _ D CLK Q Q _ D CLK Q Q _ Figure 16 1 PA 2 0 Architecture Block Diagram 16 3 2 PORTA5 The following figure describes th...

Page 68: ...0 Page 68 73 www cmostek com RD TRISA VDD RD PORTA D CLK Q Q _ WR IOCA RD IOCA Interrupt On Change D Q Q _ D Q Q _ RD PORTA Qn MCLRE MCLRE Weak Reset MCLRE Data Bus Figure 16 2 PA5 Architecture Block...

Page 69: ...ports GPIO RFDAT that is the TWI data and direct mode data input only PC4 RFCLK that is the clock line of TWI only PC2 Comparator output only PC4 but not available because it is used to control the RF...

Page 70: ...R d Z SWAPR R d 1 Swap halves reg R 0 3 R 4 7 d NONE INCR R d 1 Increment reg R 1 d Z INCRSZ R d 1 2 Increment reg skip if 0 R 1 d NONE ADDWR R d 1 Add W and reg W R d C HC Z SUBWR R d 1 Sub W from r...

Page 71: ...1 Exclu OR W and imm W I W Z R E T W I 2 Return place imm to W Stack PC I W NONE A D D W I I 1 Add imm to W W I W C HC Z SUBWI I 1 Subtract W from imm I W W C HC Z Note The TMODE register of the chip...

Page 72: ...nt Modification Record Table 18 1 Document Modification Record Sheet Version Chapter Modification descriptions Date 1 0 All Initial release 2018 05 17 1 1 4 1 14 4 1 30 Update the function description...

Page 73: ...is assumed for inaccuracies and specifications within this document are subject to change without notice The material contained herein is the exclusive property of CMOSTEK and shall not be distribute...

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