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4.1.17
TRISA
（
Addr:0x85
）
Table 4-31. TRISA Register
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Reset
1
1
1
1
1
1
1
1
Type
RW
RW
R
RW
RW
RW
RW
RW
Table 4-32. TRISA Bit Function Description
7
/PAPU
PORTA Pull-up Enable bit.
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual port latch values
6
INTEDG
Interrupt Edge Select bit
1 = Interrupt on rising edge of PA2/INT pin
0 = Interrupt on falling edge of PA2/INT pin
5
T0CS
Timer0 Clock Source Select bit
1 = Transition on PA2/T0CKI bit
0 = Internal instruction cycle clock (FOSC/2)
4
T0SE
Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on PA2/T0CKI pin
0 = Increment on low-to-high transition on PA2/T0CKI pin
3
PSA
Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned tothe Timer0 module
2:0
PS<2:0>
Prescaler Rate Select bits
BIT Value
Timer0
RATE
WDT
RATE
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1:16
1:8
100
1:32
1:16
101
1:64
1:32
110
1:128
1:64
111
1:256
1:128
Bit
Name
Function
7:6
TRISA<7:6>
PORTA<7:6> port direction Control bits
1 = Input
0 = Output
5
TRISA<5>
PORTA5 port direction Control bit
Only as input, fixed to 1
