AN202
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5.1.1
Internal Clock Mode
The oscillator mode has two independent internal oscillators, which can be configured or selected as the
system clock source.
The high frequency internal oscillator(HFINTOSC) is factory calibrated and operates at 16MHz.
The low frequency internal oscillator(LFINTOSC) is uncalibrated and operates at 32KHz. The Internal
Oscillator Frequency Select bit IRCF<2:0> can be operated to select the system clock speed via
programming.
The system clock can be selected between the external or internal clock source via System Clock Select bit
(SCS) of the OSCCON register.
Note:
The LFMOD of the OSCCON register can select LFINTOSC as 32KHz or 256KHz, but the watchdog is fixed
with 32KHz, regardless of the LFMOD value.
5.1.2
Frequency Select Bit
（
IRCF
）
The output of 16MHz HFINTOSC and 32KHz LFINTOSC is connected to the prescaler and multiplexer (see
Figure 5-1).The OSCCON register's internal oscillator frequency select bit IRCF<2:0> is used to select the
frequency output of the internal oscillator. Select one of the following eight frequencies via the software:
16MHz
8MHz
4MHz
）
(Default value after reset)
2MHz
1MHz
500KHz
250KHz
32KHz
5.1.3
Clock Switch Timing of HFINTOSC and LFINTOSC
When switching between LFINTOSC and HFINTOSC, the new oscillator may already be shut down to save
power (see Figure 5-2). In this case, there is a delay afterthe IRCF bit of the OSCCON register is modified
before the frequency selection takes place.The LTS and HTS bits of the OSCCON register will reflect the
current active status of the LFINTOSC and HFINTOSC oscillators. The frequency selection timing is as
follows:
1.
The IRCF<2:0> bit of the OSCCON register is modified.
2.
If the new clock is shut down, start a clock start-up delay.
3.
The clock switch circuit waits for the arrival of the falling edge of the current clock.
4.
Hold CLKOUT to low, the clock switch circuit waits for the arrival of the falling edge oftwo new clocks.
5.
CLKOUT is now connected with the new clock, and the HTS and LTS bits of the OSCCON register are
